Yu-hsin Wang 3aa64284b1 dev-arm: add ArmSigInterruptPin ...

ArmSigInterruptPin helps connecting ArmInterruptPin with general
interrupt pin.

Change-Id: I4235fa0714054079a111163caca8dd3985999095
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45266
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-06-02 00:19:51 +00:00

..

arch

mem: Rename "memory" variables as "mem"

2021-05-29 11:13:49 +00:00

base

base-stats,misc: Rename Stats namespace as statistics

2021-05-29 11:13:49 +00:00

cpu

cpu-o3: Prevent SW prefetches from forwarding from STQ

2021-06-01 19:27:06 +00:00

dev

dev-arm: add ArmSigInterruptPin

2021-06-02 00:19:51 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

base-stats,misc: Rename Stats namespace as statistics

2021-05-29 11:13:49 +00:00

kern

misc: Clean up ISA switching header includes.

2021-05-28 23:41:03 +00:00

learning_gem5

base-stats,misc: Rename Stats namespace as statistics

2021-05-29 11:13:49 +00:00

mem

mem: Fix Best Offset Prefetcher (BOP) learning phase code.

2021-06-01 19:36:20 +00:00

proto

python,scons: Move readCommand and compareVersions into site_scons.

2021-05-10 23:33:22 +00:00

python

base-stats,misc: Rename Stats namespace as statistics

2021-05-29 11:13:49 +00:00

sim

mem: Rename "memory" variables as "mem"

2021-05-29 11:13:49 +00:00

systemc

sim,misc: Rename Int namespace as as_int

2021-05-26 23:08:21 +00:00

Doxyfile

misc: Update version to "DEVELOP-FOR-V21.1"

2021-03-26 18:21:34 +00:00

SConscript

base: Construct debug flags on the heap

2021-05-25 00:26:28 +00:00