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In a real system, once a CPU receives an interrupt of type ExtInt, it will send an INTA message out to the I8259 sytle interrupt controllers to read the vector for that interrupt. In ye-olden-times, that would literally mean the I8259 would be in charge of the bus and would write the eight bit vector for the CPU to read. In more modern systems, the vector is transported on the system interconnect using a special message. To better approximate a real system, and to make the interrupt controllers more modular and agnostic (so the IO APIC doesn't have a I8259 pointer within it, for instance), this change adds a new special address which the I8259 can respond to on reads which will act as if it received an INTA message, and the read data will be the interrupt vector. Only the master controller, or a single device, will respond to this address, and because of its value and the fact that it's beyond the end of the 16 bit IO port address space's effective range but still within it, that address won't be generated by any other activity other than possibly a bogus address. Also by putting the special address in the IO port address space, that will make it easier to ensure that it's within the range of addresses which are routed towards the I8259 which operates off the IO port bus. This address is not yet actually used by the IO APIC or local APIC but will be shortly. Change-Id: Ib73ab4ee08531028d3540570594c552f39053a40 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55694 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This is the gem5 simulator. The main website can be found at http://www.gem5.org A good starting point is http://www.gem5.org/about, and for more information about building the simulator and getting started please see http://www.gem5.org/documentation and http://www.gem5.org/documentation/learning_gem5/introduction. To build gem5, you will need the following software: g++ or clang, Python (gem5 links in the Python interpreter), SCons, zlib, m4, and lastly protobuf if you want trace capture and playback support. Please see http://www.gem5.org/documentation/general_docs/building for more details concerning the minimum versions of these tools. Once you have all dependencies resolved, type 'scons build/<CONFIG>/gem5.opt' where CONFIG is one of the options in build_opts like ARM, NULL, MIPS, POWER, SPARC, X86, Garnet_standalone, etc. This will build an optimized version of the gem5 binary (gem5.opt) with the the specified configuration. See http://www.gem5.org/documentation/general_docs/building for more details and options. The main source tree includes these subdirectories: - build_opts: pre-made default configurations for gem5 - build_tools: tools used internally by gem5's build process. - configs: example simulation configuration scripts - ext: less-common external packages needed to build gem5 - include: include files for use in other programs - site_scons: modular components of the build system - src: source code of the gem5 simulator - system: source for some optional system software for simulated systems - tests: regression tests - util: useful utility programs and files To run full-system simulations, you may need compiled system firmware, kernel binaries and one or more disk images, depending on gem5's configuration and what type of workload you're trying to run. Many of those resources can be downloaded from http://resources.gem5.org, and/or from the git repository here: https://gem5.googlesource.com/public/gem5-resources/ If you have questions, please send mail to gem5-users@gem5.org Enjoy using gem5 and please share your modifications and extensions.