e73655d038
This patch has been generated by applying flynt to the gem5 repo (ext has been excluded) JIRA: https://gem5.atlassian.net/browse/GEM5-831 Change-Id: I0935db6223d5426b99515959bde78e374cbadb04 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68957 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
245 lines
10 KiB
Python
Executable File
245 lines
10 KiB
Python
Executable File
# Copyright (c) 2014, 2016, 2018-2019 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2003-2005 The Regents of The University of Michigan
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# Copyright (c) 2013,2015 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from .util import assignRE, commentRE, stringRE
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from .util import error
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class OperandList(object):
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"""Find all the operands in the given code block. Returns an operand
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descriptor list (instance of class OperandList)."""
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def __init__(self, parser, code):
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self.items = []
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self.bases = {}
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# delete strings and comments so we don't match on operands inside
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for regEx in (stringRE, commentRE):
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code = regEx.sub("", code)
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# search for operands
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for match in parser.operandsRE().finditer(code):
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op = match.groups()
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# regexp groups are operand full name, base, and extension
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(op_full, op_base, op_ext) = op
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# If is a elem operand, define or update the corresponding
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# vector operand
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isElem = False
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if op_base in parser.elemToVector:
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isElem = True
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elem_op = (op_base, op_ext)
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op_base = parser.elemToVector[op_base]
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op_ext = "" # use the default one
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# if the token following the operand is an assignment, this is
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# a destination (LHS), else it's a source (RHS)
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is_dest = assignRE.match(code, match.end()) != None
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is_src = not is_dest
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# see if we've already seen this one
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op_desc = self.find_base(op_base)
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if op_desc:
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if op_ext and op_ext != "" and op_desc.ext != op_ext:
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error(
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"Inconsistent extensions for operand %s: %s - %s"
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% (op_base, op_desc.ext, op_ext)
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)
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op_desc.is_src = op_desc.is_src or is_src
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op_desc.is_dest = op_desc.is_dest or is_dest
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if isElem:
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(elem_base, elem_ext) = elem_op
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found = False
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for ae in op_desc.active_elems:
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(ae_base, ae_ext) = ae
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if ae_base == elem_base:
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if ae_ext != elem_ext:
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error(
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"Inconsistent extensions for elem"
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" operand %s" % elem_base
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)
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else:
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found = True
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if not found:
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op_desc.active_elems.append(elem_op)
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else:
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# new operand: create new descriptor
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op_desc = parser.operandNameMap[op_base](
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parser, op_full, op_ext, is_src, is_dest
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)
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# if operand is a vector elem, add the corresponding vector
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# operand if not already done
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if isElem:
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op_desc.elemExt = elem_op[1]
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op_desc.active_elems = [elem_op]
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self.append(op_desc)
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self.sort()
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# enumerate source & dest register operands... used in building
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# constructor later
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regs = list(filter(lambda i: i.isReg(), self.items))
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mem = list(filter(lambda i: i.isMem(), self.items))
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srcs = list(filter(lambda r: r.is_src, regs))
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dests = list(filter(lambda r: r.is_dest, regs))
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for idx, reg in enumerate(srcs):
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reg.src_reg_idx = idx
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for idx, reg in enumerate(dests):
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reg.dest_reg_idx = idx
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self.numSrcRegs = len(srcs)
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self.numDestRegs = len(dests)
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if len(mem) > 1:
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error("Code block has more than one memory operand")
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self.memOperand = mem[0] if mem else None
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# now make a final pass to finalize op_desc fields that may depend
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# on the register enumeration
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for op_desc in self.items:
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op_desc.finalize()
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def __len__(self):
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return len(self.items)
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def __getitem__(self, index):
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return self.items[index]
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def append(self, op_desc):
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self.items.append(op_desc)
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self.bases[op_desc.base_name] = op_desc
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def find_base(self, base_name):
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# like self.bases[base_name], but returns None if not found
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# (rather than raising exception)
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return self.bases.get(base_name)
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# internal helper function for concat[Some]Attr{Strings|Lists}
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def __internalConcatAttrs(self, attr_name, filter, result):
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for op_desc in self.items:
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if filter(op_desc):
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result += getattr(op_desc, attr_name)
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return result
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# return a single string that is the concatenation of the (string)
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# values of the specified attribute for all operands
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def concatAttrStrings(self, attr_name):
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return self.__internalConcatAttrs(attr_name, lambda x: 1, "")
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# like concatAttrStrings, but only include the values for the operands
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# for which the provided filter function returns true
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def concatSomeAttrStrings(self, filter, attr_name):
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return self.__internalConcatAttrs(attr_name, filter, "")
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# return a single list that is the concatenation of the (list)
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# values of the specified attribute for all operands
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def concatAttrLists(self, attr_name):
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return self.__internalConcatAttrs(attr_name, lambda x: 1, [])
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# like concatAttrLists, but only include the values for the operands
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# for which the provided filter function returns true
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def concatSomeAttrLists(self, filter, attr_name):
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return self.__internalConcatAttrs(attr_name, filter, [])
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def sort(self):
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self.items.sort(key=lambda a: a.sort_pri)
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class SubOperandList(OperandList):
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"""Find all the operands in the given code block. Returns an operand
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descriptor list (instance of class OperandList)."""
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def __init__(self, parser, code, requestor_list):
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self.items = []
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self.bases = {}
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# delete strings and comments so we don't match on operands inside
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for regEx in (stringRE, commentRE):
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code = regEx.sub("", code)
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# search for operands
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for match in parser.operandsRE().finditer(code):
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op = match.groups()
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# regexp groups are operand full name, base, and extension
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(op_full, op_base, op_ext) = op
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# If is a elem operand, define or update the corresponding
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# vector operand
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if op_base in parser.elemToVector:
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elem_op = op_base
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op_base = parser.elemToVector[elem_op]
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# find this op in the requestor list
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op_desc = requestor_list.find_base(op_base)
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if not op_desc:
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error(
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f"Found operand {op_base} which is not in the requestor list!"
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)
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else:
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# See if we've already found this operand
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op_desc = self.find_base(op_base)
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if not op_desc:
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# if not, add a reference to it to this sub list
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self.append(requestor_list.bases[op_base])
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self.sort()
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pcs = list(filter(lambda i: i.isPCState(), self.items))
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mem = list(filter(lambda i: i.isMem(), self.items))
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if len(mem) > 1:
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error("Code block has more than one memory operand")
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part = any(p.isPCPart() for p in pcs)
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whole = any(not p.isPCPart() for p in pcs)
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if part and whole:
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error("Mixed whole and partial PC state operands")
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self.memOperand = mem[0] if mem else None
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# Whether the whole PC needs to be read so parts of it can be accessed
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self.readPC = any(i.isPCPart() for i in self.items)
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# Whether the whole PC needs to be written after parts of it were
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# changed
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self.setPC = any(i.isPCPart() and i.is_dest for i in self.items)
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# Whether this instruction manipulates the whole PC or parts of it.
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# Mixing the two is a bad idea and flagged as an error.
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self.pcPart = None
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if part:
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self.pcPart = True
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if whole:
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self.pcPart = False
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