Giacomo Travaglini 31b37a7f73 cpu: Register the ThreadContext in the CheckerCPU's ISA ...

This is needed after [1], as the Checker's ISA has an invalid (nullptr)
TC pointer.

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/29233

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I1d25096caf61f98451fca2d393d2ea1c4fca00e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46623
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-06-10 08:00:07 +00:00

..

arch

arch-arm: Remove Stage2MMU

2021-06-09 18:47:57 +00:00

base

base-stats,misc: Rename Stats namespace as statistics

2021-05-29 11:13:49 +00:00

cpu

cpu: Register the ThreadContext in the CheckerCPU's ISA

2021-06-10 08:00:07 +00:00

dev

dev: add a falsely removed if condition check in commit 03a00e5d3

2021-06-07 01:27:17 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

base-stats,misc: Rename Stats namespace as statistics

2021-05-29 11:13:49 +00:00

kern

misc: Clean up ISA switching header includes.

2021-05-28 23:41:03 +00:00

learning_gem5

base-stats,misc: Rename Stats namespace as statistics

2021-05-29 11:13:49 +00:00

mem

mem-ruby: Fix RubySystem::functionalRead with partial data

2021-06-08 07:56:09 +00:00

proto

python,scons: Move readCommand and compareVersions into site_scons.

2021-05-10 23:33:22 +00:00

python

python: Fix include of pybind

2021-06-03 13:45:10 +00:00

sim

mem: Rename "memory" variables as "mem"

2021-05-29 11:13:49 +00:00

systemc

systemc: include <typeinfo>

2021-06-07 01:29:32 +00:00

Doxyfile

misc: Update version to "DEVELOP-FOR-V21.1"

2021-03-26 18:21:34 +00:00

SConscript

base: Construct debug flags on the heap

2021-05-25 00:26:28 +00:00