Jason Lowe-Power 30200051a3 arch-x86,sim-se: Ignore the some mem syscalls ...

This makes the Linux SE mode ignore mlockall and modify_ldt. It is
needed to get ELFies working.

Change-Id: I9fce3c6a5531e5f1bb094c2d0587fa330d2892a9
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68037
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

2023-02-25 19:02:48 +00:00

..

amdgpu

arch-vega: Update API for some flat atomics

2023-02-16 03:28:25 +00:00

arm

arch-arm: Add missing <array> header in regs/misc.hh

2023-02-21 18:36:13 +00:00

generic

arch: Add a virtual method to the BaseISA to reset its ThreadContext.

2023-02-03 06:17:11 +00:00

isa_parser

arch, arch-arm, cpu: Add matrix reg support to the ISA Parser

2023-01-17 10:09:56 +00:00

mips

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

null

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00

power

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

riscv

arch-riscv: Fix incorrect trap value of instruction fault

2023-02-16 00:59:49 +00:00

sparc

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

x86

arch-x86,sim-se: Ignore the some mem syscalls

2023-02-25 19:02:48 +00:00

micro_asm_test.py

python: Apply Black formatter to Python files

2022-08-03 09:10:41 +00:00

micro_asm.py

misc: Run pre-commit run on all files in repo

2022-08-24 21:47:07 +00:00

SConscript

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

SConsopts

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00