Giacomo Travaglini 27ce721ad3 arch-arm: Pass a reference of the parent tracer to TarmacContext ...

Change-Id: I7ab0442353a8b5854bb6b50bd54dac89f83ecc1d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

2023-10-20 09:27:51 +01:00

..

amdgpu

arch-vega: Implement buffer_atomic_cmpswap (#439)

2023-10-12 07:33:40 -07:00

arm

arch-arm: Pass a reference of the parent tracer to TarmacContext

2023-10-20 09:27:51 +01:00

generic

arch-riscv: Define vlwhole/vswhole mem acceses using vlen.

2023-10-19 00:27:58 +02:00

isa_parser

misc,python: Run pre-commit run --all-files

2023-10-10 21:47:07 -07:00

mips

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

null

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00

power

arch-power: Fix reporting traps to GDB

2023-08-17 15:55:04 +01:00

riscv

arch-riscv: Define vlwhole/vswhole mem acceses using vlen.

2023-10-19 00:27:58 +02:00

sparc

misc: Fix 'unused variable' clang errors with gem5.fast

2023-05-08 22:54:06 +00:00

x86

misc: Run pre-commit run --all-files

2023-10-10 14:01:58 -07:00

micro_asm_test.py

misc,python: Run pre-commit run --all-files

2023-10-10 21:47:07 -07:00

micro_asm.py

misc,python: Run pre-commit run --all-files

2023-10-10 21:47:07 -07:00

SConscript

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

SConsopts

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00