gem5/src/cpu at 24bfda0fdf0d1f80726d8590dcd6a84d70134a53 - gem5

checker

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

memtest

cache/memtest: fixes for functional accesses.

2007-07-27 12:46:45 -07:00

o3

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

ozone

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

simple

Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.

2007-08-26 20:29:09 -07:00

trace

Merge python and x86 changes with cache branch

2007-07-26 23:15:49 -07:00

activity.cc

make our code a little more standards compliant

2007-01-26 18:48:51 -05:00

activity.hh

Update copyright.

2006-06-07 16:02:55 -04:00

base_dyn_inst_impl.hh

Fix compiler errors.

2007-06-20 19:46:45 -07:00

base_dyn_inst.hh

Add a flag to indicate an instruction triggers a syscall in SE mode.

2007-07-31 17:34:08 -07:00

base.cc

switching: turn on profiling after a switch if there's an event

2007-08-04 16:11:11 -07:00

base.hh

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

BaseCPU.py

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

cpu_models.py

Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.

2006-07-06 12:18:55 -04:00

cpuevent.cc

Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

2006-06-06 17:32:21 -04:00

cpuevent.hh

Make SPARC checkpointing work

2007-01-30 18:25:39 -05:00

exec_context.hh

*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg

2007-03-07 15:04:31 -05:00

exetrace.cc

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

exetrace.hh

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

ExeTracer.py

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

func_unit.cc

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

func_unit.hh

Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.

2006-06-16 17:52:15 -04:00

FuncUnit.py

Rename enum from OpType to OpClass so it's consistent with the

2007-06-11 23:10:58 -07:00

inst_seq.hh

fixes so that M5 will compile under solaris

2006-11-04 21:41:01 -05:00

inteltrace.cc

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

inteltrace.hh

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

IntelTrace.py

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

intr_control.cc

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

intr_control.hh

Implement Niagara I/O interface and rework interrupts

2007-03-03 17:22:47 -05:00

IntrControl.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

legiontrace.cc

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

legiontrace.hh

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

LegionTrace.py

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

m5legion_interface.h

add fsr to the list of registers we are interested in

2007-01-30 18:27:04 -05:00

nativetrace.cc

X86: Reorganize the native tracing code.

2007-08-01 12:01:51 -07:00

nativetrace.hh

X86: Reorganize the native tracing code.

2007-08-01 12:01:51 -07:00

NativeTrace.py

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

op_class.hh

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

pc_event.cc

remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault

2007-03-12 17:23:08 -04:00

pc_event.hh

Added sim/host.hh for the Addr type.

2006-11-07 05:42:15 -05:00

profile.cc

Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

2006-06-06 17:32:21 -04:00

profile.hh

Put the ProcessInfo and StackTrace objects into the ISA namespaces.

2006-11-08 00:52:04 -05:00

quiesce_event.cc

Event descriptions should not end in "event"

2007-06-30 17:45:58 -07:00

quiesce_event.hh

Update copyright.

2006-06-07 16:02:55 -04:00

SConscript

Turn the instruction tracing code into pluggable sim objects.

2007-07-28 20:30:43 -07:00

simple_thread.cc

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

simple_thread.hh

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

smt.hh

Updated Authors from bk prs info

2006-05-31 19:26:56 -04:00

static_inst.cc

Modified instruction decode method.

2007-06-14 16:52:19 -04:00

static_inst.hh

Port, StaticInst: Revert unnecessary changes.

2007-08-08 14:54:02 -04:00

thread_context.hh

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

2007-08-26 20:24:18 -07:00

thread_state.cc

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

thread_state.hh

Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.

2006-11-29 16:07:55 -05:00