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Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

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--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
This commit is contained in:
Gabe Black
2007-08-26 20:24:18 -07:00
parent f738afb865
commit 537239b278
58 changed files with 776 additions and 253 deletions
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11
src/arch/alpha/SConscript
View File

@@ -32,27 +32,28 @@
Import('*')
if env['TARGET_ISA'] == 'alpha':
Source('ev5.cc')
Source('faults.cc')
Source('floatregfile.cc')
Source('intregfile.cc')
Source('ipr.cc')
Source('miscregfile.cc')
Source('pagetable.cc')
Source('regfile.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
Source('utility.cc')
SimObject('AlphaTLB.py')
if env['FULL_SYSTEM']:
SimObject('AlphaSystem.py')
SimObject('AlphaTLB.py')
Source('ev5.cc')
Source('idle_event.cc')
Source('ipr.cc')
Source('kernel_stats.cc')
Source('osfpal.cc')
Source('pagetable.cc')
Source('stacktrace.cc')
Source('system.cc')
Source('tlb.cc')
Source('vtophys.cc')
Source('freebsd/system.cc')

75
src/arch/alpha/ev5.cc
View File

@@ -68,22 +68,6 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
delete reset;
}
////////////////////////////////////////////////////////////////////////
//
//
//
void
AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
{
for (int i = 0; i < NumInternalProcRegs; ++i) {
tc->setMiscRegNoEffect(i, 0);
}
tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
}
template <class CPU>
void
@@ -171,6 +155,24 @@ AlphaISA::MiscRegFile::getDataAsid()
return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
}
#endif
////////////////////////////////////////////////////////////////////////
//
//
//
void
AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
{
for (int i = 0; i < NumInternalProcRegs; ++i) {
tc->setMiscRegNoEffect(i, 0);
}
tc->setMiscRegNoEffect(IPR_PAL_BASE, EV5::PalBase);
tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
}
AlphaISA::MiscReg
AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
{
@@ -340,8 +342,10 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->context(old, val, tc);
#endif
break;
case AlphaISA::IPR_DTB_PTE:
@@ -368,11 +372,14 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->swpipl(ipr[idx]);
#endif
break;
case AlphaISA::IPR_DTB_CM:
#if FULL_SYSTEM
if (val & 0x18) {
if (tc->getKernelStats())
tc->getKernelStats()->mode(TheISA::Kernel::user, tc);
@@ -380,6 +387,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
if (tc->getKernelStats())
tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc);
}
#endif
case AlphaISA::IPR_ICM:
// only write two mode bits - processor mode
@@ -468,27 +476,27 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
ipr[idx] = val;
tc->getDTBPtr()->flushAddr(val,
DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
break;
case AlphaISA::IPR_DTB_TAG: {
struct AlphaISA::PTE pte;
// FIXME: granularity hints NYI...
if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
if (EV5::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
pte.ppn = EV5::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
pte.xre = EV5::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
pte.xwe = EV5::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
pte.fonr = EV5::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
pte.fonw = EV5::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
pte.asma = EV5::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
pte.asn = EV5::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
tc->getDTBPtr()->insert(val, pte);
@@ -499,20 +507,20 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
struct AlphaISA::PTE pte;
// FIXME: granularity hints NYI...
if (ITB_PTE_GH(val) != 0)
if (EV5::ITB_PTE_GH(val) != 0)
panic("PTE GH field != 0");
// write entire quad
ipr[idx] = val;
// construct PTE for new entry
pte.ppn = ITB_PTE_PPN(val);
pte.xre = ITB_PTE_XRE(val);
pte.ppn = EV5::ITB_PTE_PPN(val);
pte.xre = EV5::ITB_PTE_XRE(val);
pte.xwe = 0;
pte.fonr = ITB_PTE_FONR(val);
pte.fonw = ITB_PTE_FONW(val);
pte.asma = ITB_PTE_ASMA(val);
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
pte.fonr = EV5::ITB_PTE_FONR(val);
pte.fonw = EV5::ITB_PTE_FONW(val);
pte.asma = EV5::ITB_PTE_ASMA(val);
pte.asn = EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
@@ -538,7 +546,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
ipr[idx] = val;
tc->getITBPtr()->flushAddr(val,
ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
EV5::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
break;
default:
@@ -558,6 +566,7 @@ AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
}
}
#if FULL_SYSTEM
/**
* Check for special simulator handling of specific PAL calls.

67
src/arch/alpha/faults.cc
View File

@@ -29,13 +29,13 @@
* Kevin Lim
*/
#include "arch/alpha/ev5.hh"
#include "arch/alpha/faults.hh"
#include "arch/alpha/tlb.hh"
#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
#if FULL_SYSTEM
#include "arch/alpha/ev5.hh"
#else
#if !FULL_SYSTEM
#include "sim/process.hh"
#include "mem/page_table.hh"
#endif
@@ -83,10 +83,6 @@ FaultName DtbAlignmentFault::_name = "unalign";
FaultVect DtbAlignmentFault::_vect = 0x0301;
FaultStat DtbAlignmentFault::_count;
FaultName ItbMissFault::_name = "itbmiss";
FaultVect ItbMissFault::_vect = 0x0181;
FaultStat ItbMissFault::_count;
FaultName ItbPageFault::_name = "itbmiss";
FaultVect ItbPageFault::_vect = 0x0181;
FaultStat ItbPageFault::_count;
@@ -176,6 +172,63 @@ void ItbFault::invoke(ThreadContext * tc)
AlphaFault::invoke(tc);
}
#else
void ItbPageFault::invoke(ThreadContext * tc)
{
Process *p = tc->getProcessPtr();
Addr physaddr;
bool success = p->pTable->translate(pc, physaddr);
if(!success) {
panic("Tried to execute unmapped address %#x.\n", pc);
} else {
VAddr vaddr(pc);
VAddr paddr(physaddr);
PTE pte;
pte.tag = vaddr.vpn();
pte.ppn = paddr.vpn();
pte.xre = 15; //This can be read in all modes.
pte.xwe = 1; //This can be written only in kernel mode.
pte.asn = p->M5_pid; //Address space number.
pte.asma = false; //Only match on this ASN.
pte.fonr = false; //Don't fault on read.
pte.fonw = false; //Don't fault on write.
pte.valid = true; //This entry is valid.
tc->getITBPtr()->insert(vaddr.page(), pte);
}
}
void NDtbMissFault::invoke(ThreadContext * tc)
{
Process *p = tc->getProcessPtr();
Addr physaddr;
bool success = p->pTable->translate(vaddr, physaddr);
if(!success) {
p->checkAndAllocNextPage(vaddr);
success = p->pTable->translate(vaddr, physaddr);
}
if(!success) {
panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
} else {
VAddr paddr(physaddr);
PTE pte;
pte.tag = vaddr.vpn();
pte.ppn = paddr.vpn();
pte.xre = 15; //This can be read in all modes.
pte.xwe = 15; //This can be written in all modes.
pte.asn = p->M5_pid; //Address space number.
pte.asma = false; //Only match on this ASN.
pte.fonr = false; //Don't fault on read.
pte.fonw = false; //Don't fault on write.
pte.valid = true; //This entry is valid.
tc->getDTBPtr()->insert(vaddr.page(), pte);
}
}
#endif
} // namespace AlphaISA

39
src/arch/alpha/faults.hh
View File

@@ -35,9 +35,7 @@
#include "config/full_system.hh"
#include "sim/faults.hh"
#if FULL_SYSTEM
#include "arch/alpha/pagetable.hh"
#endif
// The design of the "name" and "vect" functions is in sim/faults.hh
@@ -140,8 +138,7 @@ class InterruptFault : public AlphaFault
class DtbFault : public AlphaFault
{
#if FULL_SYSTEM
private:
protected:
AlphaISA::VAddr vaddr;
uint32_t reqFlags;
uint64_t flags;
@@ -149,7 +146,6 @@ class DtbFault : public AlphaFault
DtbFault(AlphaISA::VAddr _vaddr, uint32_t _reqFlags, uint64_t _flags)
: vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags)
{ }
#endif
FaultName name() const = 0;
FaultVect vect() = 0;
FaultStat & countStat() = 0;
@@ -165,14 +161,15 @@ class NDtbMissFault : public DtbFault
static FaultVect _vect;
static FaultStat _count;
public:
#if FULL_SYSTEM
NDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
#endif
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
#if !FULL_SYSTEM
void invoke(ThreadContext * tc);
#endif
};
class PDtbMissFault : public DtbFault
@@ -182,11 +179,9 @@ class PDtbMissFault : public DtbFault
static FaultVect _vect;
static FaultStat _count;
public:
#if FULL_SYSTEM
PDtbMissFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
#endif
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
@@ -199,11 +194,9 @@ class DtbPageFault : public DtbFault
static FaultVect _vect;
static FaultStat _count;
public:
#if FULL_SYSTEM
DtbPageFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
#endif
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
@@ -216,11 +209,9 @@ class DtbAcvFault : public DtbFault
static FaultVect _vect;
static FaultStat _count;
public:
#if FULL_SYSTEM
DtbAcvFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
#endif
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
@@ -233,11 +224,9 @@ class DtbAlignmentFault : public DtbFault
static FaultVect _vect;
static FaultStat _count;
public:
#if FULL_SYSTEM
DtbAlignmentFault(AlphaISA::VAddr vaddr, uint32_t reqFlags, uint64_t flags)
: DtbFault(vaddr, reqFlags, flags)
{ }
#endif
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
@@ -245,7 +234,7 @@ class DtbAlignmentFault : public DtbFault
class ItbFault : public AlphaFault
{
private:
protected:
Addr pc;
public:
ItbFault(Addr _pc)
@@ -259,21 +248,6 @@ class ItbFault : public AlphaFault
#endif
};
class ItbMissFault : public ItbFault
{
private:
static FaultName _name;
static FaultVect _vect;
static FaultStat _count;
public:
ItbMissFault(Addr pc)
: ItbFault(pc)
{ }
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
};
class ItbPageFault : public ItbFault
{
private:
@@ -287,6 +261,9 @@ class ItbPageFault : public ItbFault
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
#if !FULL_SYSTEM
void invoke(ThreadContext * tc);
#endif
};
class ItbAcvFault : public ItbFault

9
src/arch/alpha/isa_traits.hh
View File

@@ -63,14 +63,13 @@ namespace AlphaISA
const Addr PageMask = ~(PageBytes - 1);
const Addr PageOffset = PageBytes - 1;
#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
//
// Translation stuff
//
const Addr PteShift = 3;
const Addr PteShift = 3;
const Addr NPtePageShift = PageShift - PteShift;
const Addr NPtePage = ULL(1) << NPtePageShift;
const Addr PteMask = NPtePage - 1;
@@ -90,6 +89,8 @@ namespace AlphaISA
// For loading... XXX This maybe could be USegEnd?? --ali
const Addr LoadAddrMask = ULL(0xffffffffff);
#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
//
// Interrupt levels
@@ -114,6 +115,8 @@ namespace AlphaISA
NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
};
#endif
// EV5 modes
enum mode_type
{
@@ -124,8 +127,6 @@ namespace AlphaISA
mode_number // number of modes
};
#endif
// Constants Related to the number of registers
const int NumIntArchRegs = 32;

25
src/arch/alpha/miscregfile.cc
View File

@@ -43,9 +43,7 @@ namespace AlphaISA
SERIALIZE_SCALAR(uniq);
SERIALIZE_SCALAR(lock_flag);
SERIALIZE_SCALAR(lock_addr);
#if FULL_SYSTEM
SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
#endif
}
void
@@ -55,9 +53,7 @@ namespace AlphaISA
UNSERIALIZE_SCALAR(uniq);
UNSERIALIZE_SCALAR(lock_flag);
UNSERIALIZE_SCALAR(lock_addr);
#if FULL_SYSTEM
UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
#endif
}
MiscReg
@@ -74,15 +70,9 @@ namespace AlphaISA
return lock_addr;
case MISCREG_INTR:
return intr_flag;
#if FULL_SYSTEM
default:
assert(misc_reg < NumInternalProcRegs);
return ipr[misc_reg];
#else
default:
panic("Attempt to read an invalid misc register!");
return 0;
#endif
}
}
@@ -100,14 +90,8 @@ namespace AlphaISA
return lock_addr;
case MISCREG_INTR:
return intr_flag;
#if FULL_SYSTEM
default:
return readIpr(misc_reg, tc);
#else
default:
panic("No faulting misc regs in SE mode!");
return 0;
#endif
}
}
@@ -130,15 +114,10 @@ namespace AlphaISA
case MISCREG_INTR:
intr_flag = val;
return;
#if FULL_SYSTEM
default:
assert(misc_reg < NumInternalProcRegs);
ipr[misc_reg] = val;
return;
#else
default:
panic("Attempt to write to an invalid misc register!");
#endif
}
}
@@ -163,11 +142,7 @@ namespace AlphaISA
intr_flag = val;
return;
default:
#if FULL_SYSTEM
setIpr(misc_reg, val, tc);
#else
panic("No registers with side effects in SE mode!");
#endif
return;
}
}

7
src/arch/alpha/miscregfile.hh
View File

@@ -34,7 +34,6 @@
#include "arch/alpha/ipr.hh"
#include "arch/alpha/types.hh"
#include "config/full_system.hh"
#include "sim/host.hh"
#include "sim/serialize.hh"
@@ -70,9 +69,7 @@ namespace AlphaISA
public:
MiscRegFile()
{
#if FULL_SYSTEM
initializeIprTable();
#endif
}
MiscReg readRegNoEffect(int misc_reg);
@@ -100,7 +97,6 @@ namespace AlphaISA
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
#if FULL_SYSTEM
protected:
typedef uint64_t InternalProcReg;
@@ -110,13 +106,10 @@ namespace AlphaISA
InternalProcReg readIpr(int idx, ThreadContext *tc);
void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
#endif
friend class RegFile;
};
#if FULL_SYSTEM
void copyIprs(ThreadContext *src, ThreadContext *dest);
#endif
}

6
src/arch/alpha/process.cc
View File

@@ -71,6 +71,12 @@ AlphaLiveProcess::startup()
argsInit(MachineBytes, VMPageSize);
threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer());
//Opperate in user mode
threadContexts[0]->setMiscRegNoEffect(IPR_ICM, 0x18);
//No super page mapping
threadContexts[0]->setMiscRegNoEffect(IPR_MCSR, 0);
//Set this to 0 for now, but it should be unique for each process
threadContexts[0]->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
}

2
src/arch/alpha/regfile.cc
View File

@@ -94,8 +94,6 @@ namespace AlphaISA
dest->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR,
src->readMiscRegNoEffect(AlphaISA::MISCREG_LOCKADDR));
#if FULL_SYSTEM
copyIprs(src, dest);
#endif
}
}

4
src/arch/alpha/utility.hh
View File

@@ -115,7 +115,6 @@ namespace AlphaISA
inline void startupCPU(ThreadContext *tc, int cpuId) {
tc->activate(0);
}
#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
//
@@ -142,8 +141,9 @@ namespace AlphaISA
RoundPage(Addr addr)
{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
void initCPU(ThreadContext *tc, int cpuId);
void initIPRs(ThreadContext *tc, int cpuId);
#if FULL_SYSTEM
void initCPU(ThreadContext *tc, int cpuId);
/**
* Function to check for and process any interrupts.

20
src/arch/mips/MipsTLB.py Normal file
View File

@@ -0,0 +1,20 @@
from m5.SimObject import SimObject
from m5.params import *
class MipsTLB(SimObject):
type = 'MipsTLB'
abstract = True
#size = Param.Int("TLB size")
class MipsDTB(MipsTLB):
type = 'MipsDTB'
cxx_namespace = 'MipsISA'
cxx_class = 'DTB'
#size = 64
class MipsITB(MipsTLB):
type = 'MipsITB'
cxx_namespace = 'MipsISA'
cxx_class = 'ITB'
#size = 64

5
src/arch/mips/SConscript
View File

@@ -33,12 +33,15 @@
Import('*')
if env['TARGET_ISA'] == 'mips':
Source('dsp.cc')
Source('faults.cc')
Source('regfile/int_regfile.cc')
Source('regfile/misc_regfile.cc')
Source('regfile/regfile.cc')
Source('tlb.cc')
Source('utility.cc')
Source('dsp.cc')
SimObject('MipsTLB.py')
if env['FULL_SYSTEM']:
#Insert Full-System Files Here

50
src/arch/mips/tlb.cc Normal file
View File

@@ -0,0 +1,50 @@
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include <cstring>
#include "arch/mips/tlb.hh"
#include "params/MipsDTB.hh"
#include "params/MipsITB.hh"
namespace MipsISA {
};
MipsISA::ITB *
MipsITBParams::create()
{
return new MipsISA::ITB(name);
}
MipsISA::DTB *
MipsDTBParams::create()
{
return new MipsISA::DTB(name);
}

53
src/arch/mips/tlb.hh Normal file
View File

@@ -0,0 +1,53 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_MIPS_TLB_HH__
#define __ARCH_MIPS_TLB_HH__
#include "sim/tlb.hh"
namespace MipsISA
{
class ITB : public GenericITB
{
public:
ITB(const std::string &name) : GenericITB(name)
{}
};
class DTB : public GenericDTB
{
public:
DTB(const std::string &name) : GenericDTB(name)
{}
};
};
#endif // __ARCH_MIPS_TLB_HH__

7
src/arch/sparc/SConscript
View File

@@ -37,18 +37,19 @@ if env['TARGET_ISA'] == 'sparc':
Source('floatregfile.cc')
Source('intregfile.cc')
Source('miscregfile.cc')
Source('pagetable.cc')
Source('regfile.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
Source('utility.cc')
SimObject('SparcTLB.py')
if env['FULL_SYSTEM']:
SimObject('SparcSystem.py')
SimObject('SparcTLB.py')
Source('pagetable.cc')
Source('stacktrace.cc')
Source('system.cc')
Source('tlb.cc')
Source('ua2005.cc')
Source('vtophys.cc')
else:

64
src/arch/sparc/faults.cc
View File

@@ -620,6 +620,70 @@ void PowerOnReset::invoke(ThreadContext * tc)
#else // !FULL_SYSTEM
void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc)
{
Process *p = tc->getProcessPtr();
Addr paddr;
bool success = p->pTable->translate(vaddr, paddr);
if(!success) {
panic("Tried to execute unmapped address %#x.\n", vaddr);
} else {
uint64_t entry = 0;
entry |= 0ULL << 1; // Not writable
entry |= 0ULL << 2; // Available in nonpriveleged mode
entry |= 0ULL << 3; // No side effects
entry |= 1ULL << 4; // Virtually cachable
entry |= 1ULL << 5; // Physically cachable
entry |= 0ULL << 6; // Not locked
entry |= mbits(paddr, 39, 13); // Physical address
entry |= 0ULL << 48; // size = 8k
entry |= 0uLL << 59; // Endianness not inverted
entry |= 0ULL << 60; // Not no fault only
entry |= 0ULL << 61; // size = 8k
entry |= 1ULL << 63; // valid
PageTableEntry PTE(entry);
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
p->M5_pid /*context id*/, false, PTE);
}
}
void FastDataAccessMMUMiss::invoke(ThreadContext *tc)
{
Process *p = tc->getProcessPtr();
Addr paddr;
bool success = p->pTable->translate(vaddr, paddr);
if(!success) {
p->checkAndAllocNextPage(vaddr);
success = p->pTable->translate(vaddr, paddr);
}
if(!success) {
panic("Tried to access unmapped address %#x.\n", vaddr);
} else {
uint64_t entry = 0;
entry |= 1ULL << 1; // Writable
entry |= 0ULL << 2; // Available in nonpriveleged mode
entry |= 0ULL << 3; // No side effects
entry |= 1ULL << 4; // Virtually cachable
entry |= 1ULL << 5; // Physically cachable
entry |= 0ULL << 6; // Not locked
entry |= mbits(paddr, 39, 13); // Physical address
entry |= 0ULL << 48; // size = 8k
entry |= 0uLL << 59; // Endianness not inverted
entry |= 0ULL << 60; // Not no fault only
entry |= 0ULL << 61; // size = 8k
entry |= 1ULL << 63; // valid
PageTableEntry PTE(entry);
Addr alignedVaddr = p->pTable->pageAlign(vaddr);
tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
p->M5_pid /*context id*/, false, PTE);
}
}
void SpillNNormal::invoke(ThreadContext *tc)
{
doNormalFault(tc, trapType(), false);

27
src/arch/sparc/faults.hh
View File

@@ -32,6 +32,7 @@
#ifndef __SPARC_FAULTS_HH__
#define __SPARC_FAULTS_HH__
#include "config/full_system.hh"
#include "sim/faults.hh"
// The design of the "name" and "vect" functions is in sim/faults.hh
@@ -42,6 +43,8 @@ namespace SparcISA
typedef uint32_t TrapType;
typedef uint32_t FaultPriority;
class ITB;
class SparcFaultBase : public FaultBase
{
public:
@@ -199,9 +202,29 @@ class PAWatchpoint : public SparcFault<PAWatchpoint> {};
class VAWatchpoint : public SparcFault<VAWatchpoint> {};
class FastInstructionAccessMMUMiss :
public SparcFault<FastInstructionAccessMMUMiss> {};
public SparcFault<FastInstructionAccessMMUMiss>
{
#if !FULL_SYSTEM
protected:
Addr vaddr;
public:
FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
{}
void invoke(ThreadContext * tc);
#endif
};
class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss> {};
class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
{
#if !FULL_SYSTEM
protected:
Addr vaddr;
public:
FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
{}
void invoke(ThreadContext * tc);
#endif
};
class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};

12
src/arch/sparc/isa_traits.hh
View File

@@ -98,12 +98,6 @@ namespace SparcISA
StaticInstPtr decodeInst(ExtMachInst);
#if FULL_SYSTEM
// I don't know what it's for, so I don't
// know what SPARC's value should be
// For loading... XXX This maybe could be USegEnd?? --ali
const Addr LoadAddrMask = ULL(0xffffffffff);
/////////// TLB Stuff ////////////
const Addr StartVAddrHole = ULL(0x0000800000000000);
const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
@@ -111,6 +105,12 @@ namespace SparcISA
const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
const Addr BytesInPageMask = ULL(0x1FFF);
#if FULL_SYSTEM
// I don't know what it's for, so I don't
// know what SPARC's value should be
// For loading... XXX This maybe could be USegEnd?? --ali
const Addr LoadAddrMask = ULL(0xffffffffff);
enum InterruptTypes
{
IT_TRAP_LEVEL_ZERO,

14
src/arch/sparc/process.cc
View File

@@ -121,6 +121,12 @@ Sparc32LiveProcess::startup()
threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
//Set the ASI register to something fixed
threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
/*
* T1 specific registers
*/
//Turn on the icache, dcache, dtb translation, and itb translation.
threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
}
void
@@ -137,7 +143,7 @@ Sparc64LiveProcess::startup()
threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0);
threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0);
//
/*
* Register window management registers
*/
@@ -163,6 +169,12 @@ Sparc64LiveProcess::startup()
threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
//Set the ASI register to something fixed
threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
/*
* T1 specific registers
*/
//Turn on the icache, dcache, dtb translation, and itb translation.
threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
}
M5_32_auxv_t::M5_32_auxv_t(int32_t type, int32_t val)

12
src/arch/sparc/tlb.cc
View File

@@ -535,7 +535,11 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
if (real)
return new InstructionRealTranslationMiss;
else
#if FULL_SYSTEM
return new FastInstructionAccessMMUMiss;
#else
return new FastInstructionAccessMMUMiss(req->getVaddr());
#endif
}
// were not priviledged accesing priv page
@@ -744,7 +748,11 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
if (real)
return new DataRealTranslationMiss;
else
#if FULL_SYSTEM
return new FastDataAccessMMUMiss;
#else
return new FastDataAccessMMUMiss(req->getVaddr());
#endif
}
@@ -853,6 +861,8 @@ handleMmuRegAccess:
return NoFault;
};
#if FULL_SYSTEM
Tick
DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
@@ -1275,6 +1285,8 @@ doMmuWriteError:
return tc->getCpuPtr()->cycles(1);
}
#endif
void
DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
{

9
src/arch/sparc/tlb.hh
View File

@@ -34,6 +34,7 @@
#include "arch/sparc/asi.hh"
#include "arch/sparc/tlb_map.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
#include "sim/sim_object.hh"
@@ -46,6 +47,12 @@ namespace SparcISA
class TLB : public SimObject
{
#if !FULL_SYSTEM
//These faults need to be able to populate the tlb in SE mode.
friend class FastInstructionAccessMMUMiss;
friend class FastDataAccessMMUMiss;
#endif
//TLB state
protected:
uint64_t c0_tsb_ps0;
@@ -183,8 +190,10 @@ class DTB : public TLB
}
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
#endif
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
// Checkpointing

3
src/arch/x86/SConscript
View File

@@ -96,6 +96,9 @@ if env['TARGET_ISA'] == 'x86':
Source('predecoder_tables.cc')
Source('regfile.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
SimObject('X86TLB.py')
if env['FULL_SYSTEM']:
# Full-system sources

75
src/arch/x86/X86TLB.py Normal file
View File

@@ -0,0 +1,75 @@
# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use of this software in source and binary forms,
# with or without modification, are permitted provided that the
# following conditions are met:
#
# The software must be used only for Non-Commercial Use which means any
# use which is NOT directed to receiving any direct monetary
# compensation for, or commercial advantage from such use. Illustrative
# examples of non-commercial use are academic research, personal study,
# teaching, education and corporate research & development.
# Illustrative examples of commercial use are distributing products for
# commercial advantage and providing services using the software for
# commercial advantage.
#
# If you wish to use this software or functionality therein that may be
# covered by patents for commercial use, please contact:
# Director of Intellectual Property Licensing
# Office of Strategy and Technology
# Hewlett-Packard Company
# 1501 Page Mill Road
# Palo Alto, California 94304
#
# Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer. Redistributions
# in binary form must reproduce the above copyright notice, this list of
# conditions and the following disclaimer in the documentation and/or
# other materials provided with the distribution. Neither the name of
# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission. No right of
# sublicense is granted herewith. Derivatives of the software and
# output created using the software may be prepared, but only for
# Non-Commercial Uses. Derivatives of the software may be shared with
# others provided: (i) the others agree to abide by the list of
# conditions herein which includes the Non-Commercial Use restrictions;
# and (ii) such Derivatives of the software include the above copyright
# notice to acknowledge the contribution from this software where
# applicable, this list of conditions and the disclaimer below.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.SimObject import SimObject
from m5.params import *
class X86TLB(SimObject):
type = 'X86TLB'
abstract = True
#size = Param.Int("TLB size")
class X86DTB(X86TLB):
type = 'X86DTB'
cxx_namespace = 'X86ISA'
cxx_class = 'DTB'
#size = 64
class X86ITB(X86TLB):
type = 'X86ITB'
cxx_namespace = 'X86ISA'
cxx_class = 'ITB'
#size = 64

77
src/arch/x86/tlb.cc Normal file
View File

@@ -0,0 +1,77 @@
/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use of this software in source and binary forms,
* with or without modification, are permitted provided that the
* following conditions are met:
*
* The software must be used only for Non-Commercial Use which means any
* use which is NOT directed to receiving any direct monetary
* compensation for, or commercial advantage from such use. Illustrative
* examples of non-commercial use are academic research, personal study,
* teaching, education and corporate research & development.
* Illustrative examples of commercial use are distributing products for
* commercial advantage and providing services using the software for
* commercial advantage.
*
* If you wish to use this software or functionality therein that may be
* covered by patents for commercial use, please contact:
* Director of Intellectual Property Licensing
* Office of Strategy and Technology
* Hewlett-Packard Company
* 1501 Page Mill Road
* Palo Alto, California 94304
*
* Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer. Redistributions
* in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution. Neither the name of
* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission. No right of
* sublicense is granted herewith. Derivatives of the software and
* output created using the software may be prepared, but only for
* Non-Commercial Uses. Derivatives of the software may be shared with
* others provided: (i) the others agree to abide by the list of
* conditions herein which includes the Non-Commercial Use restrictions;
* and (ii) such Derivatives of the software include the above copyright
* notice to acknowledge the contribution from this software where
* applicable, this list of conditions and the disclaimer below.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include <cstring>
#include "arch/x86/tlb.hh"
#include "params/X86DTB.hh"
#include "params/X86ITB.hh"
namespace X86ISA {
};
X86ISA::ITB *
X86ITBParams::create()
{
return new X86ISA::ITB(name);
}
X86ISA::DTB *
X86DTBParams::create()
{
return new X86ISA::DTB(name);
}

15
src/arch/x86/tlb.hh
View File

@@ -58,10 +58,23 @@
#ifndef __ARCH_X86_TLB_HH__
#define __ARCH_X86_TLB_HH__
#error X86 is not yet supported!
#include "sim/tlb.hh"
namespace X86ISA
{
class ITB : public GenericITB
{
public:
ITB(const std::string &name) : GenericITB(name)
{}
};
class DTB : public GenericDTB
{
public:
DTB(const std::string &name) : GenericDTB(name)
{}
};
};
#endif // __ARCH_X86_TLB_HH__

41
src/cpu/BaseCPU.py
View File

@@ -37,12 +37,14 @@ import sys
default_tracer = ExeTracer()
if build_env['FULL_SYSTEM']:
if build_env['TARGET_ISA'] == 'alpha':
from AlphaTLB import AlphaDTB, AlphaITB
if build_env['TARGET_ISA'] == 'sparc':
from SparcTLB import SparcDTB, SparcITB
if build_env['TARGET_ISA'] == 'alpha':
from AlphaTLB import AlphaDTB, AlphaITB
elif build_env['TARGET_ISA'] == 'sparc':
from SparcTLB import SparcDTB, SparcITB
elif build_env['TARGET_ISA'] == 'x86':
from X86TLB import X86DTB, X86ITB
elif build_env['TARGET_ISA'] == 'mips':
from MipsTLB import MipsDTB, MipsITB
class BaseCPU(SimObject):
type = 'BaseCPU'
@@ -57,19 +59,26 @@ class BaseCPU(SimObject):
"enable checkpoint pseudo instructions")
do_statistics_insts = Param.Bool(True,
"enable statistics pseudo instructions")
if build_env['TARGET_ISA'] == 'sparc':
dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
itb = Param.SparcITB(SparcITB(), "Instruction TLB")
elif build_env['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
else:
print "Unknown architecture, can't pick TLBs"
sys.exit(1)
else:
workload = VectorParam.Process("processes to run")
if build_env['TARGET_ISA'] == 'sparc':
dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
itb = Param.SparcITB(SparcITB(), "Instruction TLB")
elif build_env['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
elif build_env['TARGET_ISA'] == 'x86':
dtb = Param.X86DTB(X86DTB(), "Data TLB")
itb = Param.X86ITB(X86ITB(), "Instruction TLB")
elif build_env['TARGET_ISA'] == 'mips':
dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
itb = Param.MipsITB(MipsITB(), "Instruction TLB")
else:
print "Don't know what TLB to use for ISA %s" % \
build_env['TARGET_ISA']
sys.exit(1)
max_insts_all_threads = Param.Counter(0,
"terminate when all threads have reached this inst count")
max_insts_any_thread = Param.Counter(0,

8
src/cpu/checker/thread_context.hh
View File

@@ -84,15 +84,15 @@ class CheckerThreadContext : public ThreadContext
int readCpuId() { return actualTC->readCpuId(); }
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
#if FULL_SYSTEM
System *getSystemPtr() { return actualTC->getSystemPtr(); }
PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }

4
src/cpu/o3/O3CPU.py
View File

@@ -52,8 +52,8 @@ class DerivO3CPU(BaseCPU):
else:
checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
warnOnlyOnLoadError=False), "checker")
checker.itb = Parent.itb
checker.dtb = Parent.dtb
checker.itb = Parent.itb
checker.dtb = Parent.dtb
cachePorts = Param.Unsigned(200, "Cache Ports")
icache_port = Port("Instruction Port")

5
src/cpu/o3/alpha/cpu_builder.cc
View File

@@ -77,10 +77,11 @@ DerivO3CPUParams::create()
params->cpu_id = cpu_id;
params->activity = activity;
#if FULL_SYSTEM
params->system = system;
params->itb = itb;
params->dtb = dtb;
#if FULL_SYSTEM
params->system = system;
params->profile = profile;
params->do_quiesce = do_quiesce;

2
src/cpu/o3/alpha/params.hh
View File

@@ -54,10 +54,8 @@ class AlphaSimpleParams : public O3Params
{
public:
#if FULL_SYSTEM
AlphaISA::ITB *itb;
AlphaISA::DTB *dtb;
#endif
};
#endif // __CPU_O3_ALPHA_PARAMS_HH__

2
src/cpu/o3/checker_builder.cc
View File

@@ -86,9 +86,9 @@ O3CheckerParams::create()
params->progress_interval = 0;
temp2++;
#if FULL_SYSTEM
params->itb = itb;
params->dtb = dtb;
#if FULL_SYSTEM
params->system = system;
params->cpu_id = cpu_id;
params->profile = profile;

2
src/cpu/o3/cpu.cc
View File

@@ -150,10 +150,8 @@ FullO3CPU<Impl>::DeallocateContextEvent::description()
template <class Impl>
FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
: BaseO3CPU(params),
#if FULL_SYSTEM
itb(params->itb),
dtb(params->dtb),
#endif
tickEvent(this),
removeInstsThisCycle(false),
fetch(o3_cpu, params),

24
src/cpu/o3/cpu.hh
View File

@@ -113,10 +113,8 @@ class FullO3CPU : public BaseO3CPU
SwitchedOut
};
#if FULL_SYSTEM
TheISA::ITB * itb;
TheISA::DTB * dtb;
#endif
/** Overall CPU status. */
Status _status;
@@ -265,7 +263,6 @@ class FullO3CPU : public BaseO3CPU
/** Registers statistics. */
void fullCPURegStats();
#if FULL_SYSTEM
/** Translates instruction requestion. */
Fault translateInstReq(RequestPtr &req, Thread *thread)
{
@@ -284,27 +281,6 @@ class FullO3CPU : public BaseO3CPU
return this->dtb->translate(req, thread->getTC(), true);
}
#else
/** Translates instruction requestion in syscall emulation mode. */
Fault translateInstReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data read request in syscall emulation mode. */
Fault translateDataReadReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
/** Translates data write request in syscall emulation mode. */
Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
{
return thread->getProcessPtr()->pTable->translate(req);
}
#endif
/** Returns a specific port. */
Port *getPort(const std::string &if_name, int idx);

5
src/cpu/o3/fetch_impl.hh
View File

@@ -1226,7 +1226,6 @@ DefaultFetch<Impl>::fetch(bool &status_change)
// Send the fault to commit. This thread will not do anything
// until commit handles the fault. The only other way it can
// wake up is if a squash comes along and changes the PC.
#if FULL_SYSTEM
assert(numInst < fetchWidth);
// Get a sequence number.
inst_seq = cpu->getAndIncrementInstSeq();
@@ -1258,11 +1257,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
fetchStatus[tid] = TrapPending;
status_change = true;
#else // !FULL_SYSTEM
fetchStatus[tid] = TrapPending;
status_change = true;
#endif // FULL_SYSTEM
DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p",
tid, fault->name(), PC[tid]);
}

13
src/cpu/o3/mips/params.hh
View File

@@ -36,8 +36,11 @@
#include "cpu/o3/params.hh"
//Forward declarations
//class MipsDTB;
//class MipsITB;
namespace MipsISA
{
class MipsDTB;
class MipsITB;
}
class MemObject;
class Process;
class System;
@@ -53,11 +56,9 @@ class MipsSimpleParams : public O3Params
public:
MipsSimpleParams() {}
#if FULL_SYSTEM
//Full System Paramater Objects place here
MipsITB *itb;
MipsDTB *dtb;
#endif
MipsISA::ITB *itb;
MipsISA::DTB *dtb;
};
#endif // __CPU_O3_MIPS_PARAMS_HH__

5
src/cpu/o3/sparc/cpu_builder.cc
View File

@@ -78,10 +78,11 @@ DerivO3CPUParams::create()
params->cpu_id = cpu_id;
params->activity = activity;
#if FULL_SYSTEM
params->system = system;
params->itb = itb;
params->dtb = dtb;
#if FULL_SYSTEM
params->system = system;
params->profile = profile;
params->do_quiesce = do_quiesce;

2
src/cpu/o3/sparc/params.hh
View File

@@ -54,10 +54,8 @@ class SparcSimpleParams : public O3Params
{
public:
#if FULL_SYSTEM
SparcISA::ITB *itb;
SparcISA::DTB *dtb;
#endif
};
#endif // __CPU_O3_SPARC_PARAMS_HH__

2
src/cpu/o3/thread_context.hh
View File

@@ -66,13 +66,11 @@ class O3ThreadContext : public ThreadContext
/** Pointer to the thread state that this TC corrseponds to. */
O3ThreadState<Impl> *thread;
#if FULL_SYSTEM
/** Returns a pointer to the ITB. */
TheISA::ITB *getITBPtr() { return cpu->itb; }
/** Returns a pointer to the DTB. */
TheISA::DTB *getDTBPtr() { return cpu->dtb; }
#endif
/** Returns a pointer to this CPU. */
virtual BaseCPU *getCpuPtr() { return cpu; }

2
src/cpu/ozone/checker_builder.cc
View File

@@ -87,9 +87,9 @@ OzoneCheckerParams::create()
temp2++;
params->progress_interval = 0;
#if FULL_SYSTEM
params->itb = itb;
params->dtb = dtb;
#if FULL_SYSTEM
params->system = system;
params->cpu_id = cpu_id;
params->profile = profile;

8
src/cpu/ozone/cpu.hh
View File

@@ -120,15 +120,15 @@ class OzoneCPU : public BaseCPU
int readCpuId() { return thread->readCpuId(); }
TheISA::ITB *getITBPtr() { return cpu->itb; }
TheISA::DTB * getDTBPtr() { return cpu->dtb; }
#if FULL_SYSTEM
System *getSystemPtr() { return cpu->system; }
PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
TheISA::ITB *getITBPtr() { return cpu->itb; }
TheISA::DTB * getDTBPtr() { return cpu->dtb; }
TheISA::Kernel::Statistics *getKernelStats()
{ return thread->getKernelStats(); }

5
src/cpu/ozone/cpu_builder.cc
View File

@@ -79,11 +79,12 @@ DerivOzoneCPUParams::create()
params->name = name;
params->numberOfThreads = actual_num_threads;
params->itb = itb;
params->dtb = dtb;
#if FULL_SYSTEM
params->system = system;
params->cpu_id = cpu_id;
params->itb = itb;
params->dtb = dtb;
params->profile = profile;
params->do_quiesce = do_quiesce;
params->do_checkpoint_insts = do_checkpoint_insts;

4
src/cpu/ozone/cpu_impl.hh
View File

@@ -129,6 +129,8 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
thread.inSyscall = false;
thread.setStatus(ThreadContext::Suspended);
itb = p->itb;
dtb = p->dtb;
#if FULL_SYSTEM
// Setup thread state stuff.
thread.cpu = this;
@@ -137,8 +139,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
thread.quiesceEvent = new EndQuiesceEvent(tc);
system = p->system;
itb = p->itb;
dtb = p->dtb;
physmem = p->system->physmem;
if (p->profile) {

5
src/cpu/ozone/simple_cpu_builder.cc
View File

@@ -82,11 +82,12 @@ SimpleOzoneCPUParams::create()
params->name = name;
params->numberOfThreads = actual_num_threads;
params->itb = itb;
params->dtb = dtb;
#if FULL_SYSTEM
params->system = system;
params->cpu_id = cpu_id;
params->itb = itb;
params->dtb = dtb;
#else
params->workload = workload;
// params->pTable = page_table;

3
src/cpu/ozone/simple_params.hh
View File

@@ -55,9 +55,8 @@ class SimpleParams : public BaseCPU::Params
{
public:
#if FULL_SYSTEM
TheISA::ITB *itb; TheISA::DTB *dtb;
#else
#if !FULL_SYSTEM
std::vector<Process *> workload;
#endif // FULL_SYSTEM

2
src/cpu/simple/atomic.cc
View File

@@ -602,9 +602,9 @@ AtomicSimpleCPUParams::create()
params->cpu_id = cpu_id;
params->tracer = tracer;
#if FULL_SYSTEM
params->itb = itb;
params->dtb = dtb;
#if FULL_SYSTEM
params->profile = profile;
params->do_quiesce = do_quiesce;
params->do_checkpoint_insts = do_checkpoint_insts;

2
src/cpu/simple/base.cc
View File

@@ -75,7 +75,7 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p)
thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
#else
thread = new SimpleThread(this, /* thread_num */ 0, p->process,
/* asid */ 0);
p->itb, p->dtb, /* asid */ 0);
#endif // !FULL_SYSTEM
thread->setStatus(ThreadContext::Unallocated);

3
src/cpu/simple/base.hh
View File

@@ -100,10 +100,9 @@ class BaseSimpleCPU : public BaseCPU
public:
struct Params : public BaseCPU::Params
{
#if FULL_SYSTEM
TheISA::ITB *itb;
TheISA::DTB *dtb;
#else
#if !FULL_SYSTEM
Process *process;
#endif
};

2
src/cpu/simple/timing.cc
View File

@@ -727,9 +727,9 @@ TimingSimpleCPUParams::create()
params->cpu_id = cpu_id;
params->tracer = tracer;
#if FULL_SYSTEM
params->itb = itb;
params->dtb = dtb;
#if FULL_SYSTEM
params->profile = profile;
params->do_quiesce = do_quiesce;
params->do_checkpoint_insts = do_checkpoint_insts;

6
src/cpu/simple_thread.cc
View File

@@ -93,10 +93,10 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
}
}
#else
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
Process *_process, int _asid)
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid)
: ThreadState(_cpu, -1, _thread_num, _process, _asid),
cpu(_cpu)
cpu(_cpu), itb(_itb), dtb(_dtb)
{
regs.clear();
tc = new ProxyThreadContext<SimpleThread>(this);

36
src/cpu/simple_thread.hh
View File

@@ -35,6 +35,7 @@
#include "arch/isa_traits.hh"
#include "arch/regfile.hh"
#include "arch/syscallreturn.hh"
#include "arch/tlb.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
@@ -49,7 +50,6 @@ class BaseCPU;
#if FULL_SYSTEM
#include "sim/system.hh"
#include "arch/tlb.hh"
class FunctionProfile;
class ProfileNode;
@@ -109,10 +109,8 @@ class SimpleThread : public ThreadState
System *system;
#if FULL_SYSTEM
TheISA::ITB *itb;
TheISA::DTB *dtb;
#endif
// constructor: initialize SimpleThread from given process structure
#if FULL_SYSTEM
@@ -120,7 +118,8 @@ class SimpleThread : public ThreadState
TheISA::ITB *_itb, TheISA::DTB *_dtb,
bool use_kernel_stats = true);
#else
SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
#endif
SimpleThread();
@@ -149,10 +148,6 @@ class SimpleThread : public ThreadState
*/
ThreadContext *getTC() { return tc; }
#if FULL_SYSTEM
int getInstAsid() { return regs.instAsid(); }
int getDataAsid() { return regs.dataAsid(); }
Fault translateInstReq(RequestPtr &req)
{
return itb->translate(req, tc);
@@ -168,27 +163,16 @@ class SimpleThread : public ThreadState
return dtb->translate(req, tc, true);
}
#if FULL_SYSTEM
int getInstAsid() { return regs.instAsid(); }
int getDataAsid() { return regs.dataAsid(); }
void dumpFuncProfile();
Fault hwrei();
bool simPalCheck(int palFunc);
#else
Fault translateInstReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
Fault translateDataReadReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
Fault translateDataWriteReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
#endif
/*******************************************
@@ -199,13 +183,13 @@ class SimpleThread : public ThreadState
int getThreadNum() { return tid; }
#if FULL_SYSTEM
System *getSystemPtr() { return system; }
TheISA::ITB *getITBPtr() { return itb; }
TheISA::DTB *getDTBPtr() { return dtb; }
#if FULL_SYSTEM
System *getSystemPtr() { return system; }
FunctionalPort *getPhysPort() { return physPort; }
/** Return a virtual port. If no thread context is specified then a static

12
src/cpu/thread_context.hh
View File

@@ -119,13 +119,13 @@ class ThreadContext
virtual int readCpuId() = 0;
#if FULL_SYSTEM
virtual System *getSystemPtr() = 0;
virtual TheISA::ITB *getITBPtr() = 0;
virtual TheISA::DTB *getDTBPtr() = 0;
#if FULL_SYSTEM
virtual System *getSystemPtr() = 0;
virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
virtual FunctionalPort *getPhysPort() = 0;
@@ -298,13 +298,13 @@ class ProxyThreadContext : public ThreadContext
int readCpuId() { return actualTC->readCpuId(); }
#if FULL_SYSTEM
System *getSystemPtr() { return actualTC->getSystemPtr(); }
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
#if FULL_SYSTEM
System *getSystemPtr() { return actualTC->getSystemPtr(); }
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }

1
src/sim/SConscript
View File

@@ -48,6 +48,7 @@ Source('simulate.cc')
Source('startup.cc')
Source('stat_control.cc')
Source('system.cc')
Source('tlb.cc')
if env['FULL_SYSTEM']:
Source('arguments.cc')

1
src/sim/process.cc
View File

@@ -90,6 +90,7 @@ Process::Process(const string &nm,
int stderr_fd)
: SimObject(nm), system(_system)
{
M5_pid = system->allocatePID();
// initialize first 3 fds (stdin, stdout, stderr)
fd_map[STDIN_FILENO] = stdin_fd;
fd_map[STDOUT_FILENO] = stdout_fd;

4
src/sim/process.hh
View File

@@ -137,6 +137,10 @@ class Process : public SimObject
public:
PageTable *pTable;
//This id is assigned by m5 and is used to keep process' tlb entries
//separated.
uint64_t M5_pid;
private:
// file descriptor remapping support
static const int MAX_FD = 256; // max legal fd value

1
src/sim/system.cc
View File

@@ -64,6 +64,7 @@ System::System(Params *p)
virtPort(p->name + "-vport"),
#else
page_ptr(0),
next_PID(0),
#endif
memoryMode(p->mem_mode), _params(p)
{

9
src/sim/system.hh
View File

@@ -125,6 +125,15 @@ class System : public SimObject
int page_ptr;
protected:
uint64_t next_PID;
public:
uint64_t allocatePID()
{
return next_PID++;
}
#endif // FULL_SYSTEM

54
src/sim/tlb.cc Normal file
View File

@@ -0,0 +1,54 @@
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/tlb.hh"
Fault
GenericITB::translate(RequestPtr &req, ThreadContext *tc)
{
#if FULL_SYSTEM
panic("Generic ITB translation shouldn't be used in full system mode.\n");
#else
return tc->getProcessPtr()->pTable->translate(req);
#endif
}
Fault
GenericDTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
{
#if FULL_SYSTEM
panic("Generic DTB translation shouldn't be used in full system mode.\n");
#else
return tc->getProcessPtr()->pTable->translate(req);
#endif
};

66
src/sim/tlb.hh Normal file
View File

@@ -0,0 +1,66 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __SIM_TLB_HH__
#define __SIM_TLB_HH__
#include "mem/request.hh"
#include "sim/sim_object.hh"
#include "sim/faults.hh"
class ThreadContext;
class Packet;
class GenericTLB : public SimObject
{
public:
GenericTLB(const std::string &name) : SimObject(name)
{}
};
class GenericITB : public GenericTLB
{
public:
GenericITB(const std::string &name) : GenericTLB(name)
{}
Fault translate(RequestPtr &req, ThreadContext *tc);
};
class GenericDTB : public GenericTLB
{
public:
GenericDTB(const std::string &name) : GenericTLB(name)
{}
Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
};
#endif // __ARCH_SPARC_TLB_HH__