This website requires JavaScript.
Explore
Help
Sign In
derek
/
gem5
Watch
1
Star
0
Fork
0
You've already forked gem5
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
Files
202d7f62b9ea11e6b72c4b15ff818549ea14f038
gem5
/
src
/
cpu
/
simple
History
Lisa Hsu
202d7f62b9
eliminate cpu checkInterrupts bool, it is redundant and unnecessary.
...
--HG-- extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
2007-01-26 12:51:07 -05:00
..
atomic.cc
Modify ISA and staticInst to support a IsFirstMicroOp flag
2007-01-16 19:06:05 -05:00
atomic.hh
little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
2006-12-15 17:55:47 -05:00
base.cc
eliminate cpu checkInterrupts bool, it is redundant and unnecessary.
2007-01-26 12:51:07 -05:00
base.hh
Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
2006-12-12 09:58:40 -08:00
timing.cc
Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.
2006-11-29 16:07:55 -05:00
timing.hh
little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
2006-12-15 17:55:47 -05:00