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1c233ee9d23babe8964d24f386e82f64c30594da
gem5/src/cpu
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Gabe Black 1c233ee9d2 scons: Add sim_object and enums arguments to SimObject(). 
This will explicitly declare what SimObject and Enum types need to be set
up in C++, which will make importing all the SimObject modules during
the setup phase of SCons uneccessary.

Change-Id: Id2d7603daf33b236ceaa0789e2f089f589d34e62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49406
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 08:01:23 +00:00
..
checker
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
kvm
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
minor
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
o3
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
pred
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
simple
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
testers
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
trace
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
activity.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
activity.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
base.cc
arch,cpu: Stop using and remove ThreadContext::instAddr.
2021-11-30 23:30:06 +00:00
base.hh
cpu: Create a virtual BaseCPU::htmSendAbortSignal method.
2021-10-26 19:16:58 +00:00
BaseCPU.py
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
CheckerCPU.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
CPUTracers.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decode_cache.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dummy_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
DummyChecker.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
exec_context.hh
arch,cpu: Convert ExecContext::pcState to use PCStateBase.
2021-11-29 22:00:54 +00:00
exetrace.cc
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
exetrace.hh
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
func_unit.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
func_unit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnit.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inst_pb_trace.cc
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
inst_pb_trace.hh
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
inst_res.hh
cpu: Generalize the vec reg types out of InstResult.
2021-09-09 16:03:18 +00:00
inst_seq.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
InstPBTrace.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inteltrace.cc
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
inteltrace.hh
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
nativetrace.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nativetrace.hh
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
nop_static_inst.cc
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
nop_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
op_class.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pc_event.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
pc_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.hh
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
reg_class.cc
cpu: Add a mechanism which lets a reg class name its members.
2021-08-04 06:07:22 +00:00
reg_class.hh
cpu: Rename RegClassInfo to RegClass.
2021-08-09 20:04:51 +00:00
SConscript
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
simple_thread.cc
cpu: Stop including arch/decoder.hh.
2021-12-06 03:09:22 +00:00
simple_thread.hh
cpu: Stop including arch/decoder.hh.
2021-12-06 03:09:22 +00:00
smt.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst_fwd.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst.cc
cpu: Add a StaticInst::advancePC which takes a ThreadContext.
2021-12-03 03:05:41 +00:00
static_inst.hh
cpu: Add a StaticInst::advancePC which takes a ThreadContext.
2021-12-03 03:05:41 +00:00
StaticInstFlags.py
arch,cpu: Get rid of the IsMemRef StaticInst flag.
2020-09-16 12:13:08 +00:00
thread_context.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
thread_context.hh
arch,cpu: Stop using TheISA::Decoder in most places.
2021-12-06 03:09:22 +00:00
thread_state.cc
fastmodel,cpu: Eliminate the unused getVirtProxy.
2021-07-23 08:59:36 +00:00
thread_state.hh
cpu,fastmodel: Eliminate the now unnecessary initMemProxies method.
2021-07-23 08:59:54 +00:00
timebuf.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TimingExpr.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
translation.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
utils.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00