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1853d57dc3e7fdfd9dca9a4fe388a1234dd6219b
gem5/src/arch/riscv
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Bobby R. Bruce 1853d57dc3 misc: Revert "arch,cpu,mem,sim: Fold arch/locked_mem.hh..." 
This reverts commit a3f85217ab,
https://gem5-review.googlesource.com/c/public/gem5/+/48384

The reason for reverting this commit is it causes the Nightly build to
timeout: https://www.mail-archive.com/gem5-dev@gem5.org/msg40344.html

The exact cause of this failure was a stalling with the O3 processor on
ARM. The simulation reaches the following error and repeats until
timeout:

```
build/ARM/arch/arm/isa.cc:2634: warn: context 0: 2136500000 consecutive store conditional failures
```

The "realview-o3-ARM-x86_64-opt" test can replicate this:

```
./main.py run -j8 --uid
SuiteUID:tests/gem5/fs/linux/arm/test.py:realview-o3-ARM-x86_64-opt
```

Change-Id: I9e9a20753c2a25c143e6a73f58716feb41861cde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49927
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-04 04:37:49 +00:00
..
bare_metal
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
gdb-xml
scons: Turn the Blob method into a builder.
2021-08-28 04:19:40 +00:00
insts
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa
arch-riscv: Revert change-45522
2021-07-16 20:50:47 +00:00
linux
arch,kern: Use CRTP to build open flags tables, not macros.
2021-07-07 18:05:51 +00:00
regs
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decoder.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decoder.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
faults.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
faults.hh
arch-riscv: Fix illegal instruction error message
2021-08-02 22:09:09 +00:00
fp_inst.hh
arch-riscv: When an inst generates a fault, return it immediately.
2021-05-20 23:42:13 +00:00
idle_event.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
idle_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
interrupts.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa.cc
misc: Revert "arch,cpu,mem,sim: Fold arch/locked_mem.hh..."
2021-09-04 04:37:49 +00:00
isa.hh
misc: Revert "arch,cpu,mem,sim: Fold arch/locked_mem.hh..."
2021-09-04 04:37:49 +00:00
locked_mem.cc
misc: Revert "arch,cpu,mem,sim: Fold arch/locked_mem.hh..."
2021-09-04 04:37:49 +00:00
locked_mem.hh
misc: Revert "arch,cpu,mem,sim: Fold arch/locked_mem.hh..."
2021-09-04 04:37:49 +00:00
mmu.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
page_size.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable_walker.cc
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
pagetable_walker.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
pagetable.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pcstate.hh
arch,cpu: Rename arch/generic/types.hh to pcstate.hh.
2021-08-04 04:15:21 +00:00
pma_checker.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pma_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
PMAChecker.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pmp.cc
arch-riscv: Fixed a bug in pmp.cc
2021-09-03 16:54:56 +00:00
pmp.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
PMP.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pra_constants.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
process.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
reg_abi.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
reg_abi.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
remote_gdb.cc
scons: Turn the Blob method into a builder.
2021-08-28 04:19:40 +00:00
remote_gdb.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RiscvFsWorkload.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RiscvInterrupts.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RiscvISA.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RiscvMMU.py
arch: Add TypeTLB Param in BaseTLB
2021-07-28 08:13:09 +00:00
RiscvSeWorkload.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RiscvTLB.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
SConscript
misc: Revert "arch,cpu,mem,sim: Fold arch/locked_mem.hh..."
2021-09-04 04:37:49 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
se_workload.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stacktrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
tlb.cc
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
tlb.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
types.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
utility.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
vecregs.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00