Gabe Black 16fa9f9812 arch,cpu: Get rid of is*Reg() methods in RegId. ...

These bake in the existing set of RegClass values and are not flexible
or scalable.

Change-Id: I107460cd82960d96916d1644403b7635820045a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45226
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-05-10 20:03:38 +00:00

..

probes

misc: Fix coding style for struct's opening braces

2021-03-19 20:57:24 +00:00

atomic.cc

arch,cpu,kern,sim: Eliminate the utility.hh switching header.

2021-03-22 21:01:58 +00:00

atomic.hh

cpu: Make the NonCachingSimpleCPU use a back door for fetch.

2020-11-10 13:43:19 +00:00

AtomicSimpleCPU.py

cpu: Delete authors lists from the cpu directory.

2020-02-17 21:51:23 +00:00

base.cc

misc: Collapse all uses of DTRACE(x) to Debug::x.

2021-05-10 20:00:48 +00:00

base.hh

cpu,arch: Move the zero register index into RegClassInfo.

2021-04-29 12:48:47 +00:00

BaseSimpleCPU.py

arch, mem, cpu, systemc: Remove Python 2.7 glue code

2021-01-27 10:18:43 +00:00

exec_context.hh

arch,cpu: Get rid of is*Reg() methods in RegId.

2021-05-10 20:03:38 +00:00

noncaching.cc

cpu: Make the NonCachingSimpleCPU use a back door for fetch.

2020-11-10 13:43:19 +00:00

noncaching.hh

cpu: Make the NonCachingSimpleCPU use a back door for fetch.

2020-11-10 13:43:19 +00:00

NonCachingSimpleCPU.py

misc: Standardize the way create() constructs SimObjects.

2020-10-14 12:06:44 +00:00

SConscript

cpu: Delete authors lists from the cpu directory.

2020-02-17 21:51:23 +00:00

SConsopts

cpu: Delete authors lists from the cpu directory.

2020-02-17 21:51:23 +00:00

timing.cc

arch,cpu,kern,sim: Eliminate the utility.hh switching header.

2021-03-22 21:01:58 +00:00

timing.hh

misc: Fix coding style for struct's opening braces

2021-03-19 20:57:24 +00:00

TimingSimpleCPU.py

cpu: Delete authors lists from the cpu directory.

2020-02-17 21:51:23 +00:00