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gem5/src/cpu
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Mahyar Samani eb25cbd9d7 cpu: Adding GUPSGen ClockedObject. 
This patch adds the code base to implement GUPSGen which is a
ClockedObject that creates read/write requests to the memory
to update elements in an array. The choosing of elements in
the array follow a random distribution. Each element is read
from and return as GUPSGen implements a key-value store program.
Specifications are found in HPCC website from RandomAccess
benchmark. link below.
https://icl.cs.utk.edu/projectsfiles/hpcc/RandomAccess/

Change-Id: I5c07f230bee317fff2cceec04d15d0218e8ede9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47439
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 22:19:25 +00:00
..
checker
cpu: Generalize the vec reg types out of InstResult.
2021-09-09 16:03:18 +00:00
kvm
cpu-kvm: Reinitialize threads on drainResume
2021-09-19 17:32:59 +00:00
minor
arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.
2021-09-28 19:56:01 +00:00
o3
misc: Fix hdf5 stats + test
2021-10-12 06:03:21 +00:00
pred
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
simple
arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.
2021-09-28 19:56:01 +00:00
testers
cpu: Adding GUPSGen ClockedObject.
2021-10-13 22:19:25 +00:00
trace
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
activity.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
activity.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
base.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
base.hh
misc: Replace THE_ISA macro with IS_NULL_ISA.
2021-08-04 21:04:22 +00:00
BaseCPU.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
CheckerCPU.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
CPUTracers.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decode_cache.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dummy_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
DummyChecker.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
exec_context.hh
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
exetrace.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
exetrace.hh
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
func_unit.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
func_unit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnit.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inst_pb_trace.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
inst_pb_trace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inst_res.hh
cpu: Generalize the vec reg types out of InstResult.
2021-09-09 16:03:18 +00:00
inst_seq.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
InstPBTrace.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inteltrace.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inteltrace.hh
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
nativetrace.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nativetrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nop_static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nop_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
op_class.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pc_event.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
pc_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.hh
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
reg_class.cc
cpu: Add a mechanism which lets a reg class name its members.
2021-08-04 06:07:22 +00:00
reg_class.hh
cpu: Rename RegClassInfo to RegClass.
2021-08-09 20:04:51 +00:00
SConscript
cpu: Stop excluding the protobuf tracer for x86.
2021-10-13 20:22:37 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
simple_thread.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
simple_thread.hh
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
smt.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst_fwd.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
StaticInstFlags.py
arch,cpu: Get rid of the IsMemRef StaticInst flag.
2020-09-16 12:13:08 +00:00
thread_context.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_context.hh
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
thread_state.cc
fastmodel,cpu: Eliminate the unused getVirtProxy.
2021-07-23 08:59:36 +00:00
thread_state.hh
cpu,fastmodel: Eliminate the now unnecessary initMemProxies method.
2021-07-23 08:59:54 +00:00
timebuf.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TimingExpr.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
translation.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
utils.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00