Gabe Black 15df63624b arch-x86: Add some DPRINTFs to the TLB. ...

These DPRINTFs are related to segmentation handling when in 32 bit
protected mode.

Change-Id: I47eb2bc834fc748b5d01d85e02ea8b3f6e03091b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55246
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2022-02-15 08:54:11 +00:00

..

amdgpu

arch-vega: Fix global 64-bit calcAddr with SGPR base

2022-01-20 16:03:23 +00:00

arm

arch,cpu: Turn (read|set)*Reg into inline helpers.

2022-02-14 21:48:37 +00:00

generic

arch: Remove TheISA::VecElem from arch/vecregs.hh.

2022-02-01 18:48:55 +00:00

isa_parser

misc: Linearlize VecElem indexing.

2022-01-21 23:05:47 +00:00

mips

arch: Remove TheISA::VecElem from arch/vecregs.hh.

2022-02-01 18:48:55 +00:00

null

arch: Remove TheISA::VecElem from arch/vecregs.hh.

2022-02-01 18:48:55 +00:00

power

arch: Remove TheISA::VecElem from arch/vecregs.hh.

2022-02-01 18:48:55 +00:00

riscv

arch-riscv,sim-se: correct the spelling of sendto

2022-02-11 03:33:02 +00:00

sparc

arch: Remove TheISA::VecElem from arch/vecregs.hh.

2022-02-01 18:48:55 +00:00

x86

arch-x86: Add some DPRINTFs to the TLB.

2022-02-15 08:54:11 +00:00

micro_asm_test.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

micro_asm.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

SConscript

scons: Exclude parsetab.py when collecting python deps.

2022-02-10 16:56:49 +00:00

SConsopts

scons: Turn the ISA and GPU ISA lists into construction variables.

2021-08-07 03:12:56 +00:00