0e5aa3da42
This change makes an MMU cache per TLB port as is required by x86 and RISC-V. Change-Id: I79cf82ab18d31b81d3ec7060501f2642f21b630b Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49364 Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
The gem5 Components Library
IMPORTANT NOTE: This is a Work-In-Process Documentation. This will be expanded and completed in later revisions of the components library.
This is a high-level overview of what this library is.
Philosophy
Like the Zen of Python, the gem5 Components Library has a set of guiding principles. Note, these are note rules, and they are meant to be bent if needed (but maybe not broken).
Components are extensible, not configurable
We prefer extensibility instead of configurability.
Instead of each component taking many different parameters, we have decided to make many different components.
For instance, instead of having one core component which takes a parameter of the type (e.g., in-order or out-of-order), we specify multiple different components, an InOrderCPU and an OutOfOrder CPU.
Components use easy to remember names
We prefer longer and easier to remember names than shorter or jargon names.
Structure of the components library
Boards
Processors
Memories
Cache hierarchies
Contributing to the components library
Code style
- Use Black to format your code.
- Docstring should follow the ReST style and Sphinx