Giacomo Travaglini 098feb4042 arch-arm: Fix WFI sleeping in secure mode ...

The CPU should not sleep with a pending virtual interrupt
if secure mode EL2 is supported (FEAT_SEL2)

Change-Id: Ib71c4a09d76a790331cf6750da45f83694946aee
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

2023-11-21 13:39:41 +00:00

..

amdgpu

gpu-compute: Fix typo with GPUTLB print (#529)

2023-11-13 14:40:27 -08:00

arm

arch-arm: Fix WFI sleeping in secure mode

2023-11-21 13:39:41 +00:00

generic

arch-riscv: Define vlwhole/vswhole mem acceses using vlen.

2023-10-19 00:27:58 +02:00

isa_parser

misc,python: Run pre-commit run --all-files

2023-10-10 21:47:07 -07:00

mips

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

null

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00

power

arch-power: Fix reporting traps to GDB

2023-08-17 15:55:04 +01:00

riscv

arch-riscv: Add overrides to RISC-V Interrupts class (#568)

2023-11-15 18:36:15 -08:00

sparc

misc: Fix 'unused variable' clang errors with gem5.fast

2023-05-08 22:54:06 +00:00

x86

misc: Run pre-commit run --all-files

2023-10-10 14:01:58 -07:00

micro_asm_test.py

misc,python: Run pre-commit run --all-files

2023-10-10 21:47:07 -07:00

micro_asm.py

misc,python: Run pre-commit run --all-files

2023-10-10 21:47:07 -07:00

SConscript

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

SConsopts

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00