Ali Saidi f317227b4e hopefully the final hacky change to make the bus bridge work ok ...

cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here

src/mem/bridge.cc:
src/mem/bridge.hh:
    hopefully the final hacky change to make the bus bridge work ok

--HG--
extra : convert_revision : 62cbc65c74d1a84199f0a376546ec19994c5899c

2007-05-15 17:39:50 -04:00

..

arch

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

base

total should be the sum of the vector result of an operation,

2007-05-11 11:47:18 -07:00

cpu

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

dev

couple more bug fixes for intel nic

2007-05-14 16:37:00 -04:00

doxygen

Fix up doxygen.

2006-08-14 19:25:07 -04:00

kern

change the way dprintf works so the cache accesses required to fulfill the dprintf aren't show in between the Cycle: name:

2007-05-01 18:14:16 -04:00

mem

hopefully the final hacky change to make the bus bridge work ok

2007-05-15 17:39:50 -04:00

python

Move full CPU sim object stuff into the encumbered directory

2007-05-11 15:01:44 -07:00

sim

update for new reschedule semantics

2007-05-09 22:34:54 -04:00

unittest

Quick program to time how long ccprintf takes to write

2007-02-07 22:02:09 -08:00

Doxyfile

Fix up doxygen.

2006-08-14 19:25:07 -04:00

SConscript

Completely re-work how the scons framework incorporates swig

2007-04-12 21:20:04 -07:00