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update for new reschedule semantics

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--HG--
extra : convert_revision : 8c18b2513d638f67cc096e7f1483b47390a374ca
This commit is contained in:
Ali Saidi
2007-05-09 22:34:54 -04:00
parent ff55888575
commit 9dfbea68a2
6 changed files with 21 additions and 37 deletions
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16
src/dev/i8254xGBe.cc
View File

@@ -727,12 +727,8 @@ IGbE::RxDescCache::pktComplete()
if (igbe->regs.rdtr.delay()) {
DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n",
igbe->regs.rdtr.delay() * igbe->intClock());
if (igbe->rdtrEvent.scheduled())
igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() *
igbe->intClock());
else
igbe->rdtrEvent.schedule(curTick + igbe->regs.rdtr.delay() *
igbe->intClock());
igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() *
igbe->intClock(),true);
}
if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) {
@@ -946,12 +942,8 @@ IGbE::TxDescCache::pktComplete()
DPRINTF(EthernetDesc, "Descriptor had IDE set\n");
if (igbe->regs.tidv.idv()) {
DPRINTF(EthernetDesc, "setting tidv\n");
if (igbe->tidvEvent.scheduled())
igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
igbe->intClock());
else
igbe->tidvEvent.schedule(curTick + igbe->regs.tidv.idv() *
igbe->intClock());
igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
igbe->intClock(), true);
}
if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {

5
src/dev/io_device.cc
View File

@@ -111,10 +111,7 @@ DmaPort::recvTiming(PacketPtr pkt)
else if (backoffTime < device->maxBackoffDelay)
backoffTime <<= 1;
if (backoffEvent.scheduled())
backoffEvent.reschedule(curTick + backoffTime);
else
backoffEvent.schedule(curTick + backoffTime);
backoffEvent.reschedule(curTick + backoffTime, true);
DPRINTF(DMA, "Backoff time set to %d ticks\n", backoffTime);

5
src/dev/ns_gige.cc
View File

@@ -2310,10 +2310,7 @@ NSGigE::transferDone()
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
if (txEvent.scheduled())
txEvent.reschedule(curTick + cycles(1));
else
txEvent.schedule(curTick + cycles(1));
txEvent.reschedule(curTick + cycles(1), true);
}
bool

5
src/dev/sinic.cc
View File

@@ -1199,10 +1199,7 @@ Device::transferDone()
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
if (txEvent.scheduled())
txEvent.reschedule(curTick + cycles(1));
else
txEvent.schedule(curTick + cycles(1));
txEvent.reschedule(curTick + cycles(1), true);
}
bool

17
src/sim/eventq.hh
View File

@@ -210,7 +210,8 @@ class Event : public Serializable, public FastAlloc
void schedule(Tick t);
/// Reschedule the event with the current priority
void reschedule(Tick t);
// always parameter means to schedule if not already scheduled
void reschedule(Tick t, bool always = false);
/// Remove the event from the current schedule
void deschedule();
@@ -402,16 +403,22 @@ Event::deschedule()
}
inline void
Event::reschedule(Tick t)
Event::reschedule(Tick t, bool always)
{
assert(scheduled());
clearFlags(Squashed);
assert(scheduled() || always);
#if TRACING_ON
when_scheduled = curTick;
#endif
_when = t;
queue->reschedule(this);
if (scheduled()) {
clearFlags(Squashed);
queue->reschedule(this);
} else {
setFlags(Scheduled);
queue->schedule(this);
}
}
inline void

10
src/sim/pseudo_inst.cc
View File

@@ -87,10 +87,7 @@ namespace PseudoInst
Tick resume = curTick + Clock::Int::ns * ns;
if (quiesceEvent->scheduled())
quiesceEvent->reschedule(resume);
else
quiesceEvent->schedule(resume);
quiesceEvent->reschedule(resume, true);
DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
tc->getCpuPtr()->name(), ns, resume);
@@ -110,10 +107,7 @@ namespace PseudoInst
Tick resume = curTick + tc->getCpuPtr()->cycles(cycles);
if (quiesceEvent->scheduled())
quiesceEvent->reschedule(resume);
else
quiesceEvent->schedule(resume);
quiesceEvent->reschedule(resume, true);
DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
tc->getCpuPtr()->name(), cycles, resume);