Ali Saidi f317227b4e hopefully the final hacky change to make the bus bridge work ok ...

cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here

src/mem/bridge.cc:
src/mem/bridge.hh:
    hopefully the final hacky change to make the bus bridge work ok

--HG--
extra : convert_revision : 62cbc65c74d1a84199f0a376546ec19994c5899c

2007-05-15 17:39:50 -04:00

..

cache

add uglyiness to fix dmas

2007-05-14 16:14:59 -04:00

config

Backing in more changsets, getting closer to compile

2006-06-28 14:35:00 -04:00

bridge.cc

hopefully the final hacky change to make the bus bridge work ok

2007-05-15 17:39:50 -04:00

bridge.hh

hopefully the final hacky change to make the bus bridge work ok

2007-05-15 17:39:50 -04:00

bus.cc

undo my previous bus change, it can make the bus deadlock.. so it still constantly reschedules itself

2007-05-09 22:23:01 -04:00

bus.hh

fix partial writes with a functional memory hack

2007-05-07 14:42:03 -04:00

dram.cc

make our code a little more standards compliant

2007-01-26 18:48:51 -05:00

dram.hh

Use PacketPtr everywhere

2006-10-20 00:10:12 -07:00

mem_object.cc

stop m5 from leaking like a sieve

2007-03-08 18:57:15 -05:00

mem_object.hh

stop m5 from leaking like a sieve

2007-03-08 18:57:15 -05:00

packet_access.hh

Make byteswap work correctly on Twin??_t types.

2007-03-07 17:46:04 +00:00

packet.cc

fix partial writes with a functional memory hack

2007-05-07 14:42:03 -04:00

packet.hh

Move all of the parameters of the Root SimObject so they are

2007-03-06 11:13:43 -08:00

page_table.cc

Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures.

2007-03-07 20:04:46 +00:00

page_table.hh

add code to serialize se structures. Lisa is working on the python side of things and will test

2006-10-17 19:38:36 -04:00

physical.cc

some forgotten commits

2007-02-12 18:40:08 -05:00

physical.hh

rename store conditional stuff as extra data so it can be used for conditional swaps as well

2007-02-12 13:06:30 -05:00

port_impl.hh

Put the ProcessInfo and StackTrace objects into the ISA namespaces.

2006-11-08 00:52:04 -05:00

port.cc

The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter.

2007-04-04 13:56:38 -04:00

port.hh

fix partial writes with a functional memory hack

2007-05-07 14:42:03 -04:00

request.hh

Move all of the parameters of the Root SimObject so they are

2007-03-06 11:13:43 -08:00

SConscript

Rework the way SCons recurses into subdirectories, making it

2007-03-10 23:00:54 -08:00

tport.cc

add a backoff algorithm when nacks are received by devices

2007-05-09 18:20:24 -04:00

tport.hh

Merge ktlim@zizzer:/bk/newmem

2006-10-31 14:37:19 -05:00

translating_port.cc

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

translating_port.hh

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

vport.cc

implement vtophys and 32bit gdb support

2007-02-18 19:57:46 -05:00

vport.hh

implement vtophys and 32bit gdb support

2007-02-18 19:57:46 -05:00