Giacomo Travaglini 05d733d0cd arch-arm: Generalize KVM Gic state copying logic ...

By moving the Gic state copying logic from the MuxingKvmGic to the
BaseGic we allow different Gic releases (e.g Gicv2, Gicv3) to override
the implementation accoding to their personal architectural state

It is also possible to use the same logic outside of the KVM
context

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I88d6fca69a9b61a889c5ec53221404b8396cc12d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55607
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2022-02-01 10:42:57 +00:00

..

amdgpu

arch-vega: Fix global 64-bit calcAddr with SGPR base

2022-01-20 16:03:23 +00:00

arm

arch-arm: Generalize KVM Gic state copying logic

2022-02-01 10:42:57 +00:00

generic

scons: Add sim_object and enums arguments to SimObject().

2021-12-08 08:01:23 +00:00

isa_parser

misc: Linearlize VecElem indexing.

2022-01-21 23:05:47 +00:00

mips

cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.

2022-01-12 15:59:27 +00:00

null

arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

2021-09-28 19:56:01 +00:00

power

cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.

2022-01-12 15:59:27 +00:00

riscv

arch-riscv: Fix (c.)addiw sign-extension behaviour

2022-01-28 10:39:09 +00:00

sparc

cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.

2022-01-12 15:59:27 +00:00

x86

misc: Linearlize VecElem indexing.

2022-01-21 23:05:47 +00:00

micro_asm_test.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

micro_asm.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

SConscript

arch: Delete the decoder.hh switching header file.

2021-12-06 03:09:22 +00:00

SConsopts

scons: Turn the ISA and GPU ISA lists into construction variables.

2021-08-07 03:12:56 +00:00