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032ea9b2db870ad9b2a039f8c4020e38f5dd7f62
gem5/src/cpu
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Lisa Hsu 032ea9b2db the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in. 
src/arch/sparc/interrupts.hh:
    fill in how we do interrupts on sparc a little bit.

    1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU.
    2) fill in getInterrupts() a little bit.

    also, update the bitfield access to be HPSTATE::hpriv, etc.
src/arch/sparc/ua2005.cc:
    1) update formatting
    2) change the way interrupts are done to use the new way to tickle the CPU.
src/cpu/base.cc:
src/cpu/base.hh:
    overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value.

--HG--
extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
2007-01-08 18:18:28 -05:00
..
checker
Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
2006-12-12 09:58:40 -08:00
memtest
little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
2006-12-15 17:55:47 -05:00
o3
Fix up previous commit to proper logic.
2006-12-30 13:21:25 -05:00
ozone
don't use (*activeThreads).begin(), use activeThreads->blah().
2006-12-20 22:20:11 -08:00
simple
little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
2006-12-15 17:55:47 -05:00
trace
Move main control from C++ into Python.
2006-06-09 23:01:31 -04:00
activity.cc
Update copyright.
2006-06-07 16:02:55 -04:00
activity.hh
Update copyright.
2006-06-07 16:02:55 -04:00
base_dyn_inst_impl.hh
Add in support for LL/SC in the O3 CPU. Needs to be fully tested.
2006-10-23 14:00:07 -04:00
base_dyn_inst.hh
Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
2006-12-12 09:58:40 -08:00
base.cc
the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
2007-01-08 18:18:28 -05:00
base.hh
the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
2007-01-08 18:18:28 -05:00
cpu_models.py
Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.
2006-07-06 12:18:55 -04:00
cpuevent.cc
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
2006-06-06 17:32:21 -04:00
cpuevent.hh
Formatting
2007-01-03 10:13:45 -08:00
exec_context.hh
Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
2006-12-12 09:58:40 -08:00
exetrace.cc
change when legion-lock causes the simulation to die. It now happens after two consuctive differences since we compare stuff
2007-01-08 17:11:10 -05:00
exetrace.hh
add code to operate in lockstep with legion
2006-11-07 15:51:37 -05:00
func_unit.cc
Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.
2006-06-16 17:52:15 -04:00
func_unit.hh
Reorganization to move FuncUnit, FUDesc, and OpDesc out of the encumbered directory and into the normal cpu directory.
2006-06-16 17:52:15 -04:00
inst_seq.hh
fixes so that M5 will compile under solaris
2006-11-04 21:41:01 -05:00
intr_control.cc
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
2006-06-06 17:32:21 -04:00
intr_control.hh
Updated Authors from bk prs info
2006-05-31 19:26:56 -04:00
m5legion_interface.h
Compare legion and m5 tlbs for differences
2006-12-27 14:35:23 -05:00
op_class.cc
Updated Authors from bk prs info
2006-05-31 19:26:56 -04:00
op_class.hh
Merge ktlim@zizzer:/bk/newmem
2006-06-02 18:19:50 -04:00
pc_event.cc
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
2006-06-06 17:32:21 -04:00
pc_event.hh
Added sim/host.hh for the Addr type.
2006-11-07 05:42:15 -05:00
profile.cc
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
2006-06-06 17:32:21 -04:00
profile.hh
Put the ProcessInfo and StackTrace objects into the ISA namespaces.
2006-11-08 00:52:04 -05:00
quiesce_event.cc
Add Quiesce trace flag to track CPU quiesce/wakeup events.
2006-10-21 23:32:14 -07:00
quiesce_event.hh
Update copyright.
2006-06-07 16:02:55 -04:00
SConscript
Update the Memtester, commit a config file/test for it.
2006-10-09 00:26:10 -04:00
simple_thread.cc
Update Virtual and Physical ports.
2006-11-19 17:43:03 -05:00
simple_thread.hh
Get rid of unused lock code.
2006-12-12 02:21:03 -05:00
smt.hh
Updated Authors from bk prs info
2006-05-31 19:26:56 -04:00
static_inst.cc
StaticInst support for microcode
2006-10-12 17:32:02 -04:00
static_inst.hh
StaticInst support for microcode
2006-10-12 17:32:02 -04:00
thread_context.hh
Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.
2006-11-29 16:07:55 -05:00
thread_state.cc
Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.
2006-11-29 16:07:55 -05:00
thread_state.hh
Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.
2006-11-29 16:07:55 -05:00