a8b2d66661
at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early. --HG-- extra : convert_revision : f237363eababb2aad67e5b41670cf40be048a042
731 lines
30 KiB
C++
731 lines
30 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Lisa Hsu
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* Nathan Binkert
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* Steve Raasch
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*/
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#include <fstream>
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#include <iomanip>
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#include <sys/ipc.h>
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#include <sys/shm.h>
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#include "arch/regfile.hh"
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#include "arch/utility.hh"
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#include "base/loader/symtab.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/static_inst.hh"
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#include "sim/param.hh"
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#include "sim/system.hh"
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#if FULL_SYSTEM
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#include "arch/tlb.hh"
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#endif
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//XXX This is temporary
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#include "arch/isa_specific.hh"
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#include "cpu/m5legion_interface.h"
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using namespace std;
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using namespace TheISA;
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#if THE_ISA == SPARC_ISA && FULL_SYSTEM
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static int diffcount = 0;
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#endif
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namespace Trace {
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SharedData *shared_data = NULL;
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}
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////////////////////////////////////////////////////////////////////////
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//
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// Methods for the InstRecord object
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//
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#if THE_ISA == SPARC_ISA
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inline char * genCenteredLabel(int length, char * buffer, char * label)
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{
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int labelLength = strlen(label);
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assert(labelLength <= length);
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int leftPad = (length - labelLength) / 2;
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int rightPad = length - leftPad - labelLength;
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char format[64];
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sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad);
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sprintf(buffer, format, "", label, "");
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return buffer;
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}
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inline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b)
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{
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ccprintf(os, " %16s | %#018x %s %#-018x \n",
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title, a, (a == b) ? "|" : "X", b);
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}
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inline void printColumnLabels(ostream & os)
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{
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static char * regLabel = genCenteredLabel(16, new char[17], "Register");
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static char * m5Label = genCenteredLabel(18, new char[18], "M5");
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static char * legionLabel = genCenteredLabel(18, new char[18], "Legion");
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ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel);
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ccprintf(os, "--------------------+-----------------------+-----------------------\n");
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}
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inline void printSectionHeader(ostream & os, char * name)
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{
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char sectionString[70];
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genCenteredLabel(69, sectionString, name);
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ccprintf(os, "====================================================================\n");
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ccprintf(os, "%69s\n", sectionString);
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ccprintf(os, "====================================================================\n");
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}
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inline void printLevelHeader(ostream & os, int level)
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{
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char sectionString[70];
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char levelName[70];
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sprintf(levelName, "Trap stack level %d", level);
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genCenteredLabel(69, sectionString, levelName);
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ccprintf(os, "====================================================================\n");
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ccprintf(os, "%69s\n", sectionString);
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ccprintf(os, "====================================================================\n");
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}
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#endif
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void
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Trace::InstRecord::dump(ostream &outs)
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{
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if (flags[PRINT_REG_DELTA])
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{
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#if THE_ISA == SPARC_ISA
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//Don't print what happens for each micro-op, just print out
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//once at the last op, and for regular instructions.
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if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
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{
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static uint64_t regs[32] = {
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0};
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static uint64_t ccr = 0;
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static uint64_t y = 0;
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static uint64_t floats[32];
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uint64_t newVal;
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static const char * prefixes[4] = {"G", "O", "L", "I"};
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outs << hex;
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outs << "PC = " << thread->readNextPC();
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outs << " NPC = " << thread->readNextNPC();
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newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
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if(newVal != ccr)
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{
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outs << " CCR = " << newVal;
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ccr = newVal;
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}
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newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
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if(newVal != y)
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{
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outs << " Y = " << newVal;
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y = newVal;
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}
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for(int y = 0; y < 4; y++)
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{
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for(int x = 0; x < 8; x++)
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{
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int index = x + 8 * y;
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newVal = thread->readIntReg(index);
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if(regs[index] != newVal)
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{
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outs << " " << prefixes[y] << dec << x << " = " << hex << newVal;
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regs[index] = newVal;
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}
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}
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}
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for(int y = 0; y < 32; y++)
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{
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newVal = thread->readFloatRegBits(2 * y, 64);
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if(floats[y] != newVal)
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{
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outs << " F" << dec << (2 * y) << " = " << hex << newVal;
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floats[y] = newVal;
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}
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}
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outs << dec << endl;
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}
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#endif
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}
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else if (flags[INTEL_FORMAT]) {
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#if FULL_SYSTEM
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bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
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#else
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bool is_trace_system = true;
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#endif
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if (is_trace_system) {
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ccprintf(outs, "%7d ) ", cycle);
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outs << "0x" << hex << PC << ":\t";
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if (staticInst->isLoad()) {
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outs << "<RD 0x" << hex << addr;
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outs << ">";
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} else if (staticInst->isStore()) {
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outs << "<WR 0x" << hex << addr;
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outs << ">";
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}
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outs << endl;
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}
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} else {
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if (flags[PRINT_CYCLE])
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ccprintf(outs, "%7d: ", cycle);
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outs << thread->getCpuPtr()->name() << " ";
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if (flags[TRACE_MISSPEC])
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outs << (misspeculating ? "-" : "+") << " ";
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if (flags[PRINT_THREAD_NUM])
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outs << "T" << thread->getThreadNum() << " : ";
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std::string sym_str;
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Addr sym_addr;
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if (debugSymbolTable
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&& debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
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&& flags[PC_SYMBOL]) {
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if (PC != sym_addr)
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sym_str += csprintf("+%d", PC - sym_addr);
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outs << "@" << sym_str << " : ";
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}
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else {
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outs << "0x" << hex << PC << " : ";
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}
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//
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// Print decoded instruction
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//
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#if defined(__GNUC__) && (__GNUC__ < 3)
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// There's a bug in gcc 2.x library that prevents setw()
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// from working properly on strings
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string mc(staticInst->disassemble(PC, debugSymbolTable));
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while (mc.length() < 26)
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mc += " ";
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outs << mc;
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#else
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outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
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#endif
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outs << " : ";
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if (flags[PRINT_OP_CLASS]) {
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outs << opClassStrings[staticInst->opClass()] << " : ";
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}
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if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
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outs << " D=";
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#if 0
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if (data_status == DataDouble)
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ccprintf(outs, "%f", data.as_double);
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else
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ccprintf(outs, "%#018x", data.as_int);
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#else
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ccprintf(outs, "%#018x", data.as_int);
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#endif
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}
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if (flags[PRINT_EFF_ADDR] && addr_valid)
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outs << " A=0x" << hex << addr;
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if (flags[PRINT_INT_REGS] && regs_valid) {
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for (int i = 0; i < TheISA::NumIntRegs;)
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for (int j = i + 1; i <= j; i++)
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ccprintf(outs, "r%02d = %#018x%s", i,
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iregs->regs.readReg(i),
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((i == j) ? "\n" : " "));
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outs << "\n";
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}
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if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
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outs << " FetchSeq=" << dec << fetch_seq;
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if (flags[PRINT_CP_SEQ] && cp_seq_valid)
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outs << " CPSeq=" << dec << cp_seq;
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//
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// End of line...
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//
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outs << endl;
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}
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#if THE_ISA == SPARC_ISA && FULL_SYSTEM
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// Compare
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if (flags[LEGION_LOCKSTEP])
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{
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bool compared = false;
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bool diffPC = false;
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bool diffCC = false;
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bool diffInst = false;
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bool diffRegs = false;
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bool diffTpc = false;
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bool diffTnpc = false;
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bool diffTstate = false;
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bool diffTt = false;
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bool diffTba = false;
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bool diffHpstate = false;
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bool diffHtstate = false;
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bool diffHtba = false;
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bool diffPstate = false;
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bool diffY = false;
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bool diffCcr = false;
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bool diffTl = false;
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bool diffGl = false;
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bool diffAsi = false;
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bool diffPil = false;
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bool diffCwp = false;
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bool diffCansave = false;
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bool diffCanrestore = false;
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bool diffOtherwin = false;
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bool diffCleanwin = false;
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bool diffTlb = false;
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Addr m5Pc, lgnPc;
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if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
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while (!compared) {
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if (shared_data->flags == OWN_M5) {
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m5Pc = PC & TheISA::PAddrImplMask;
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lgnPc = shared_data->pc & TheISA::PAddrImplMask;
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if (lgnPc != m5Pc)
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diffPC = true;
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if (shared_data->cycle_count !=
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thread->getCpuPtr()->instCount())
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diffCC = true;
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if (shared_data->instruction !=
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(SparcISA::MachInst)staticInst->machInst) {
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diffInst = true;
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}
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for (int i = 0; i < TheISA::NumIntArchRegs; i++) {
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if (thread->readIntReg(i) != shared_data->intregs[i]) {
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diffRegs = true;
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}
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}
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uint64_t oldTl = thread->readMiscReg(MISCREG_TL);
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if (oldTl != shared_data->tl)
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diffTl = true;
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for (int i = 1; i <= MaxTL; i++) {
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thread->setMiscReg(MISCREG_TL, i);
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if (thread->readMiscReg(MISCREG_TPC) !=
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shared_data->tpc[i-1])
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diffTpc = true;
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if (thread->readMiscReg(MISCREG_TNPC) !=
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shared_data->tnpc[i-1])
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diffTnpc = true;
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if (thread->readMiscReg(MISCREG_TSTATE) !=
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shared_data->tstate[i-1])
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diffTstate = true;
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if (thread->readMiscReg(MISCREG_TT) !=
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shared_data->tt[i-1])
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diffTt = true;
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if (thread->readMiscReg(MISCREG_HTSTATE) !=
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shared_data->htstate[i-1])
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diffHtstate = true;
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}
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thread->setMiscReg(MISCREG_TL, oldTl);
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if(shared_data->tba != thread->readMiscReg(MISCREG_TBA))
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diffTba = true;
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//When the hpstate register is read by an instruction,
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//legion has bit 11 set. When it's in storage, it doesn't.
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//Since we don't directly support seperate interpretations
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//of the registers like that, the bit is always set to 1 and
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//we just don't compare it. It's not supposed to matter
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//anyway.
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if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE))
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diffHpstate = true;
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if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA))
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diffHtba = true;
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if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE))
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diffPstate = true;
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if(shared_data->y != thread->readMiscReg(MISCREG_Y))
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diffY = true;
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if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR))
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diffCcr = true;
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if(shared_data->gl != thread->readMiscReg(MISCREG_GL))
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diffGl = true;
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if(shared_data->asi != thread->readMiscReg(MISCREG_ASI))
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diffAsi = true;
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if(shared_data->pil != thread->readMiscReg(MISCREG_PIL))
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diffPil = true;
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if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP))
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diffCwp = true;
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if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
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diffCansave = true;
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if(shared_data->canrestore !=
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thread->readMiscReg(MISCREG_CANRESTORE))
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diffCanrestore = true;
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if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
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diffOtherwin = true;
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if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
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diffCleanwin = true;
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for (int i = 0; i < 64; i++) {
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if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i))
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diffTlb = true;
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if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i))
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diffTlb = true;
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}
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if ((diffPC || diffCC || diffInst || diffRegs || diffTpc ||
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diffTnpc || diffTstate || diffTt || diffHpstate ||
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diffHtstate || diffHtba || diffPstate || diffY ||
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diffCcr || diffTl || diffGl || diffAsi || diffPil ||
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diffCwp || diffCansave || diffCanrestore ||
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diffOtherwin || diffCleanwin || diffTlb)
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&& !((staticInst->machInst & 0xC1F80000) == 0x81D00000)
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&& !(((staticInst->machInst & 0xC0000000) == 0xC0000000)
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&& shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1)
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) {
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|
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outs << "Differences found between M5 and Legion:";
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if (diffPC)
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outs << " [PC]";
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|
if (diffCC)
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|
outs << " [CC]";
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|
if (diffInst)
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|
outs << " [Instruction]";
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|
if (diffRegs)
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|
outs << " [IntRegs]";
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|
if (diffTpc)
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outs << " [Tpc]";
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|
if (diffTnpc)
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outs << " [Tnpc]";
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|
if (diffTstate)
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|
outs << " [Tstate]";
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|
if (diffTt)
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outs << " [Tt]";
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|
if (diffHpstate)
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|
outs << " [Hpstate]";
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|
if (diffHtstate)
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|
outs << " [Htstate]";
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if (diffHtba)
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|
outs << " [Htba]";
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|
if (diffPstate)
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|
outs << " [Pstate]";
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|
if (diffY)
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|
outs << " [Y]";
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|
if (diffCcr)
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|
outs << " [Ccr]";
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|
if (diffTl)
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|
outs << " [Tl]";
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|
if (diffGl)
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|
outs << " [Gl]";
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|
if (diffAsi)
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|
outs << " [Asi]";
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|
if (diffPil)
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outs << " [Pil]";
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if (diffCwp)
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outs << " [Cwp]";
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if (diffCansave)
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outs << " [Cansave]";
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if (diffCanrestore)
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outs << " [Canrestore]";
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if (diffOtherwin)
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outs << " [Otherwin]";
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if (diffCleanwin)
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outs << " [Cleanwin]";
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if (diffTlb)
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outs << " [Tlb]";
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|
outs << endl << endl;
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|
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outs << right << setfill(' ') << setw(15)
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<< "M5 PC: " << "0x"<< setw(16) << setfill('0')
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<< hex << m5Pc << endl;
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|
outs << setfill(' ') << setw(15)
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<< "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
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<< lgnPc << endl << endl;
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outs << right << setfill(' ') << setw(15)
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<< "M5 CC: " << "0x"<< setw(16) << setfill('0')
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<< hex << thread->getCpuPtr()->instCount() << endl;
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outs << setfill(' ') << setw(15)
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<< "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex
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<< shared_data->cycle_count << endl << endl;
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|
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|
outs << setfill(' ') << setw(15)
|
|
<< "M5 Inst: " << "0x"<< setw(8)
|
|
<< setfill('0') << hex << staticInst->machInst
|
|
<< staticInst->disassemble(m5Pc, debugSymbolTable)
|
|
<< endl;
|
|
|
|
StaticInstPtr legionInst =
|
|
StaticInst::decode(makeExtMI(shared_data->instruction,
|
|
thread));
|
|
outs << setfill(' ') << setw(15)
|
|
<< " Legion Inst: "
|
|
<< "0x" << setw(8) << setfill('0') << hex
|
|
<< shared_data->instruction
|
|
<< legionInst->disassemble(lgnPc, debugSymbolTable)
|
|
<< endl << endl;
|
|
|
|
printSectionHeader(outs, "General State");
|
|
printColumnLabels(outs);
|
|
printRegPair(outs, "HPstate",
|
|
thread->readMiscReg(MISCREG_HPSTATE),
|
|
shared_data->hpstate | (1 << 11));
|
|
printRegPair(outs, "Htba",
|
|
thread->readMiscReg(MISCREG_HTBA),
|
|
shared_data->htba);
|
|
printRegPair(outs, "Pstate",
|
|
thread->readMiscReg(MISCREG_PSTATE),
|
|
shared_data->pstate);
|
|
printRegPair(outs, "Y",
|
|
thread->readMiscReg(MISCREG_Y),
|
|
shared_data->y);
|
|
printRegPair(outs, "Ccr",
|
|
thread->readMiscReg(MISCREG_CCR),
|
|
shared_data->ccr);
|
|
printRegPair(outs, "Tl",
|
|
thread->readMiscReg(MISCREG_TL),
|
|
shared_data->tl);
|
|
printRegPair(outs, "Gl",
|
|
thread->readMiscReg(MISCREG_GL),
|
|
shared_data->gl);
|
|
printRegPair(outs, "Asi",
|
|
thread->readMiscReg(MISCREG_ASI),
|
|
shared_data->asi);
|
|
printRegPair(outs, "Pil",
|
|
thread->readMiscReg(MISCREG_PIL),
|
|
shared_data->pil);
|
|
printRegPair(outs, "Cwp",
|
|
thread->readMiscReg(MISCREG_CWP),
|
|
shared_data->cwp);
|
|
printRegPair(outs, "Cansave",
|
|
thread->readMiscReg(MISCREG_CANSAVE),
|
|
shared_data->cansave);
|
|
printRegPair(outs, "Canrestore",
|
|
thread->readMiscReg(MISCREG_CANRESTORE),
|
|
shared_data->canrestore);
|
|
printRegPair(outs, "Otherwin",
|
|
thread->readMiscReg(MISCREG_OTHERWIN),
|
|
shared_data->otherwin);
|
|
printRegPair(outs, "Cleanwin",
|
|
thread->readMiscReg(MISCREG_CLEANWIN),
|
|
shared_data->cleanwin);
|
|
outs << endl;
|
|
for (int i = 1; i <= MaxTL; i++) {
|
|
printLevelHeader(outs, i);
|
|
printColumnLabels(outs);
|
|
thread->setMiscReg(MISCREG_TL, i);
|
|
printRegPair(outs, "Tpc",
|
|
thread->readMiscReg(MISCREG_TPC),
|
|
shared_data->tpc[i-1]);
|
|
printRegPair(outs, "Tnpc",
|
|
thread->readMiscReg(MISCREG_TNPC),
|
|
shared_data->tnpc[i-1]);
|
|
printRegPair(outs, "Tstate",
|
|
thread->readMiscReg(MISCREG_TSTATE),
|
|
shared_data->tstate[i-1]);
|
|
printRegPair(outs, "Tt",
|
|
thread->readMiscReg(MISCREG_TT),
|
|
shared_data->tt[i-1]);
|
|
printRegPair(outs, "Htstate",
|
|
thread->readMiscReg(MISCREG_HTSTATE),
|
|
shared_data->htstate[i-1]);
|
|
}
|
|
thread->setMiscReg(MISCREG_TL, oldTl);
|
|
outs << endl;
|
|
|
|
printSectionHeader(outs, "General Purpose Registers");
|
|
static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
|
|
for(int y = 0; y < 4; y++)
|
|
{
|
|
for(int x = 0; x < 8; x++)
|
|
{
|
|
char label[8];
|
|
sprintf(label, "%s%d", regtypes[y], x);
|
|
printRegPair(outs, label,
|
|
thread->readIntReg(y*8+x),
|
|
shared_data->intregs[y*8+x]);
|
|
/*outs << regtypes[y] << x << " " ;
|
|
outs << "0x" << hex << setw(16)
|
|
<< thread->readIntReg(y*8+x);
|
|
if (thread->readIntReg(y*8 + x)
|
|
!= shared_data->intregs[y*8+x])
|
|
outs << " X ";
|
|
else
|
|
outs << " | ";
|
|
outs << "0x" << setw(16) << hex
|
|
<< shared_data->intregs[y*8+x]
|
|
<< endl;*/
|
|
}
|
|
}
|
|
printColumnLabels(outs);
|
|
char label[8];
|
|
for (int x = 0; x < 64; x++) {
|
|
if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) ||
|
|
thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) {
|
|
sprintf(label, "I-TLB:%02d", x);
|
|
printRegPair(outs, label, thread->getITBPtr()->TteRead(x), shared_data->itb[x]);
|
|
}
|
|
}
|
|
for (int x = 0; x < 64; x++) {
|
|
if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) ||
|
|
thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) {
|
|
sprintf(label, "D-TLB:%02d", x);
|
|
printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), shared_data->dtb[x]);
|
|
}
|
|
}
|
|
thread->getITBPtr()->dumpAll();
|
|
thread->getDTBPtr()->dumpAll();
|
|
|
|
diffcount++;
|
|
if (diffcount > 2)
|
|
fatal("Differences found between Legion and M5\n");
|
|
} else
|
|
diffcount = 0;
|
|
|
|
compared = true;
|
|
shared_data->flags = OWN_LEGION;
|
|
}
|
|
} // while
|
|
} // if not microop
|
|
}
|
|
#endif
|
|
}
|
|
|
|
|
|
vector<bool> Trace::InstRecord::flags(NUM_BITS);
|
|
string Trace::InstRecord::trace_system;
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// Parameter space for per-cycle execution address tracing options.
|
|
// Derive from ParamContext so we can override checkParams() function.
|
|
//
|
|
class ExecutionTraceParamContext : public ParamContext
|
|
{
|
|
public:
|
|
ExecutionTraceParamContext(const string &_iniSection)
|
|
: ParamContext(_iniSection)
|
|
{
|
|
}
|
|
|
|
void checkParams(); // defined at bottom of file
|
|
};
|
|
|
|
ExecutionTraceParamContext exeTraceParams("exetrace");
|
|
|
|
Param<bool> exe_trace_spec(&exeTraceParams, "speculative",
|
|
"capture speculative instructions", true);
|
|
|
|
Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle",
|
|
"print cycle number", true);
|
|
Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass",
|
|
"print op class", true);
|
|
Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread",
|
|
"print thread number", true);
|
|
Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr",
|
|
"print effective address", true);
|
|
Param<bool> exe_trace_print_data(&exeTraceParams, "print_data",
|
|
"print result data", true);
|
|
Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs",
|
|
"print all integer regs", false);
|
|
Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
|
|
"print fetch sequence number", false);
|
|
Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
|
|
"print correct-path sequence number", false);
|
|
Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta",
|
|
"print which registers changed to what", false);
|
|
Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
|
|
"Use symbols for the PC if available", true);
|
|
Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
|
|
"print trace in intel compatible format", false);
|
|
Param<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep",
|
|
"Compare sim state to legion state every cycle",
|
|
false);
|
|
Param<string> exe_trace_system(&exeTraceParams, "trace_system",
|
|
"print trace of which system (client or server)",
|
|
"client");
|
|
|
|
|
|
//
|
|
// Helper function for ExecutionTraceParamContext::checkParams() just
|
|
// to get us into the InstRecord namespace
|
|
//
|
|
void
|
|
Trace::InstRecord::setParams()
|
|
{
|
|
flags[TRACE_MISSPEC] = exe_trace_spec;
|
|
|
|
flags[PRINT_CYCLE] = exe_trace_print_cycle;
|
|
flags[PRINT_OP_CLASS] = exe_trace_print_opclass;
|
|
flags[PRINT_THREAD_NUM] = exe_trace_print_thread;
|
|
flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr;
|
|
flags[PRINT_EFF_ADDR] = exe_trace_print_data;
|
|
flags[PRINT_INT_REGS] = exe_trace_print_iregs;
|
|
flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
|
|
flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
|
|
flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta;
|
|
flags[PC_SYMBOL] = exe_trace_pc_symbol;
|
|
flags[INTEL_FORMAT] = exe_trace_intel_format;
|
|
flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep;
|
|
trace_system = exe_trace_system;
|
|
|
|
// If were going to be in lockstep with Legion
|
|
// Setup shared memory, and get otherwise ready
|
|
if (flags[LEGION_LOCKSTEP]) {
|
|
int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
|
|
if (shmfd < 0)
|
|
fatal("Couldn't get shared memory fd. Is Legion running?");
|
|
|
|
shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
|
|
if (shared_data == (SharedData*)-1)
|
|
fatal("Couldn't allocate shared memory");
|
|
|
|
if (shared_data->flags != OWN_M5)
|
|
fatal("Shared memory has invalid owner");
|
|
|
|
if (shared_data->version != VERSION)
|
|
fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
|
|
shared_data->version);
|
|
|
|
// step legion forward one cycle so we can get register values
|
|
shared_data->flags = OWN_LEGION;
|
|
}
|
|
}
|
|
|
|
void
|
|
ExecutionTraceParamContext::checkParams()
|
|
{
|
|
Trace::InstRecord::setParams();
|
|
}
|
|
|