00008b725c
Some of the Vega scalar instructions (S_SETPC_B64, S_RFE_B64, S_CBRANCH_JOIN, and S_SET_GPR_IDX_IDX) do not use the SDST scalar destination register. However, Vega's operand encoding function for the SOP1 instruction type's class assumed all instructions used the destination register, which results in an assert failure for these instructions. To resolve this, this commit updates the Vega SOP1 operand encoder to ignore the destination register for these specific instructions. Change-Id: I2f0d830f6264fc7f47c0694a2fd5da5d33d2ea0b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60649 Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Matthew Poremba <matthew.poremba@amd.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>