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  • 53d2c9398e Move Linux/Tru64 architecture independent code into kern/* leaving dependent code making way for solaris linux syscall emu. Ali Saidi 2006-02-18 23:44:22 -05:00
  • a48c24b61e Support NNPC and branch instructions ... Outputs to decoder.cc correctly Korey Sewell 2006-02-18 23:17:45 -05:00
  • bf4fb61fa1 Merge gblack@m5.eecs.umich.edu:/bk/multiarch into ewok.(none):/home/gblack/m5/multiarch Gabe Black 2006-02-18 20:58:26 -05:00
  • db40f25616 Changed the isa from a class to a namespace, untemplated StaticInst and StaticInstPtr, converted things to using TheISA, cleaned up some header file paths, and improved the system which pulls header files from the appropriate architecture. Gabe Black 2006-02-18 20:58:08 -05:00
  • a611b81003 few changes for nate: 1) cosmetic - removing visibility of meta axes except for the tick labels. 2) unless subticklabels defined, don't do meta axes. (instead of assuming if you have 3D graph, do meta axes) Lisa Hsu 2006-02-18 20:10:42 -05:00
  • 6cf0ba8495 remove print statements Lisa Hsu 2006-02-18 18:39:19 -05:00
  • 71bf22165a more changes for subtick labels. Lisa Hsu 2006-02-18 17:29:43 -05:00
  • b00468ce8b Merge zizzer:/bk/m5 into zed.eecs.umich.edu:/z/hsul/work/m5/clean Lisa Hsu 2006-02-18 17:24:37 -05:00
  • ef14fd4ad3 Now you can have sublabels for every bar using the self.xsubticklabels parameter. Lisa Hsu 2006-02-18 17:24:23 -05:00
  • bd17580928 changes from mergedmem Korey Sewell 2006-02-18 14:38:23 -05:00
  • 159e334531 use string name to figure out if we have a "AndLink" instruction Korey Sewell 2006-02-18 04:17:11 -05:00
  • 6bf71f96f3 MIPS generates ISA code through scons '.../decoder.cc'!!! Now, must create g++ compilable code ... Korey Sewell 2006-02-18 03:12:04 -05:00
  • dd11b2c4ff Get rid of deque (poor memory allocation), switch them over to lists. Kevin Lim 2006-02-17 15:07:48 -05:00
  • d6a330ebb9 Remove fake fault. Switch fault pointers to const pointers to prevent them from accidentally being changed. Fix some coding style. Kevin Lim 2006-02-16 14:55:15 -05:00
  • c7624c26e7 Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-new Kevin Lim 2006-02-16 12:03:44 -05:00
  • 485568efa9 Fixes to handle generating the initiateAcc and completeAcc functions a little more cleanly. Kevin Lim 2006-02-16 11:55:28 -05:00
  • 7446238118 Get ISA parser to at least include all the ISA correctly ... crashes with "None" error Korey Sewell 2006-02-16 02:51:04 -05:00
  • e7d16b0aef Merge zizzer:/bk/multiarch into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch Korey Sewell 2006-02-16 02:40:04 -05:00
  • 7c9ea671af file name changes ... minor ISA changes Korey Sewell 2006-02-16 02:39:46 -05:00
  • 00f451cc02 Some changes which weren't needed before doing a bk pull were needed afterwards, for some reason. Gabe Black 2006-02-16 02:08:13 -05:00
  • b161d2a731 Merge gblack@m5.eecs.umich.edu:/bk/multiarch into ewok.(none):/home/gblack/m5/multiarch Gabe Black 2006-02-16 01:25:48 -05:00
  • 10c79efe55 Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA. Gabe Black 2006-02-16 01:22:51 -05:00
  • 7f17f1f2df Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch Gabe Black 2006-02-15 23:24:35 -05:00
  • d142788172 More compilation fixes. Should we add a proxy_port that does the v->p address translation? Should the proxy port return a fault on translation errors, if we add one? Ron Dreslinski 2006-02-15 22:05:23 -05:00
  • b8a2d1e5c7 More progress toward compiling... partly by fixing things, partly by ignoring CPU models that don't currently compile. Steve Reinhardt 2006-02-15 17:52:49 -05:00
  • 091e6b72cf Slightly fix compiling. Now decoder.cc fails on trying to set some flags that no longer exist (PF_EXCLUSIVE, EVICT_NEXT). Kevin Lim 2006-02-15 16:40:02 -05:00
  • 90def9ea9e Changes to start making the tree use the new memory system. Trying to compile decoder.cc but fails still. Ron Dreslinski 2006-02-15 14:53:02 -05:00
  • 7f114ca419 Many changes that make the new mem system compile. Now to convert the rest of the tree to use the new mem system. Ron Dreslinski 2006-02-15 14:21:09 -05:00
  • a0cdf213ab ... Korey Sewell 2006-02-15 14:08:54 -05:00
  • 2d04f18674 Gives separate methods for initiating and completing a memory access, which will be helpful for the merged memory model. Kevin Lim 2006-02-15 13:05:21 -05:00
  • 7b42d61f13 Merge zizzer:/bk/m5 into pb15.local:/Users/ali/work/m5.head Ali Saidi 2006-02-15 01:27:06 -05:00
  • 18a0fa3e0c endian fixes and compiles on mac os x Ali Saidi 2006-02-15 01:23:13 -05:00
  • aee1bf5873 Merge zizzer:/bk/multiarch into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch Korey Sewell 2006-02-14 22:43:26 -05:00
  • 23bbec6a34 another big step to a parsable ISA ... no errors after I used a symbolic link for arch/alpha/main.isa to test my files ... Korey Sewell 2006-02-14 22:43:14 -05:00
  • 5830200d78 trying to get ISA to parse correctly ... Korey Sewell 2006-02-14 21:26:01 -05:00
  • 7826fcd09d New files to fix building the SPARC_SE and MIPS_SE isa_parser.py generated files. Gabe Black 2006-02-14 20:13:08 -05:00
  • 085b73fe44 Fixed a path in the alpha isa description. Gabe Black 2006-02-14 03:57:42 -05:00
  • 9f584bcc6f Merge zizzer:/bk/multiarch into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch Korey Sewell 2006-02-14 02:12:39 -05:00
  • d7ac2b56c2 make MIPS MT instructions decodable ... Korey Sewell 2006-02-14 02:03:14 -05:00
  • 19e5efed03 Pseudo instructions are now passed whatever instructions they need by the decoder, rather than extracting them explicitly. This lets most of the pseudo instruction code to be shared across architectures. Gabe Black 2006-02-12 17:38:10 -05:00
  • 2c5e03550a Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh. Gabe Black 2006-02-12 12:40:58 -05:00
  • 4d4c105ac5 Merge gblack@m5.eecs.umich.edu:/bk/multiarch into ewok.(none):/home/gblack/m5/multiarch Gabe Black 2006-02-12 12:17:51 -05:00
  • 47a065d9f0 vptr.hh: Rename: arch/alpha/vptr.hh -> sim/vptr.hh Gabe Black 2006-02-12 12:14:14 -05:00
  • 94590a4dba Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch Gabe Black 2006-02-12 11:38:26 -05:00
  • 79613686f0 Polishing of isa_parser.py internal operand handling, resulting in minor change to syntax of 'def operands' in ISA descriptions. Steve Reinhardt 2006-02-12 00:31:19 -05:00
  • 8f2e096275 Minor cleanup of operand type and traits code in isa_parser.py. Steve Reinhardt 2006-02-11 21:26:49 -05:00
  • 3cc6c59582 Add keyword parameters and list-valued arguments to instruction format functions in ISA description language. Steve Reinhardt 2006-02-11 15:11:00 -05:00
  • 59ba3d463c fix #if. I wonder why my compiler had no issues. Even though it is clearly wrong Ali Saidi 2006-02-11 11:01:51 -05:00
  • 96d6ac441c hello world works on a BE host for a LE guest Ali Saidi 2006-02-11 00:55:36 -05:00
  • f2e97427be Merge zizzer:/bk/m5 into pb15.local:/Users/ali/work/m5.head Ali Saidi 2006-02-10 20:06:44 -05:00
  • b070018266 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch Gabe Black 2006-02-10 17:35:26 -05:00
  • ac6240896e confused an ifdef with an if Ali Saidi 2006-02-10 14:59:37 -05:00
  • a86a3fa525 Merge zizzer:/bk/m5 into udhcp-macvpn-776.public.engin.umich.edu:/Users/ali/work/m5.head Ali Saidi 2006-02-10 14:38:15 -05:00
  • fb7899aa68 fix problems on darwin/*BSD for syscall emulation mode Ali Saidi 2006-02-10 14:21:32 -05:00
  • 3923eec0ef Change how memory operands are handled in ISA descriptions. Should enable implementation of split-phase timing loads with new memory model. May create slight timing differences under FullCPU, as I believe we were not handling software prefetches correctly before when the split MemAcc/Exec model was used. I haven't looked into this in any detail though. Steve Reinhardt 2006-02-10 09:12:55 -05:00
  • 2865768112 Merge zizzer:/bk/multiarch into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch Korey Sewell 2006-02-10 03:31:13 -05:00
  • 5cfc5e8080 The first fully coded version of decoder.isa!!!!! ================================================= -every MIPS32 ISA is represented with some type of code block. -any instruction that doesnt have a code block would be of format WarnUnimpl. Examples of the ones I am waiting on further info to implement are the TLB register insts, memory consistency instructions (ll,sc,etc.) and software debug insts. Korey Sewell 2006-02-10 03:27:19 -05:00
  • dd473ecd57 Split Alpha ISA description into multiple files (thanks to Gabe's include feature!). Steve Reinhardt 2006-02-09 23:02:38 -05:00
  • fb90b1dd13 Minor cleanup of include-handling code in isa_parser.py. Steve Reinhardt 2006-02-09 22:27:41 -05:00
  • 2c528d5865 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 into zizzer.eecs.umich.edu:/z/stever/bk/m5 Steve Reinhardt 2006-02-09 14:58:56 -05:00
  • 730ee42ab8 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 into zizzer.eecs.umich.edu:/z/stever/bk/m5 Steve Reinhardt 2006-02-09 14:51:56 -05:00
  • 879aaa5569 Change how isa_parser.py generates C++ names for isa_desc operands. Steve Reinhardt 2006-02-09 14:51:37 -05:00
  • 5102de8321 Merge gblack@m5.eecs.umich.edu:/bk/multiarch into ewok.(none):/home/gblack/m5/multiarch Gabe Black 2006-02-09 14:48:10 -05:00
  • ecfe2cc91f Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch Gabe Black 2006-02-09 14:37:44 -05:00
  • 7d9b93d825 Changed the filenames to the new standard again Gabe Black 2006-02-09 13:56:24 -05:00
  • a0f65246bf Merge gblack@m5.eecs.umich.edu:/bk/multiarch into ewok.(none):/home/gblack/m5/multiarch Gabe Black 2006-02-09 13:07:00 -05:00
  • d3c1cc9f15 A fix for SConscript so it will work with newer versions of scons Gabe Black 2006-02-09 13:06:47 -05:00
  • fb10300c4f more code for instructions... Mainly for coprocessor0 and coprocessor1 move instructions Korey Sewell 2006-02-09 04:26:04 -05:00
  • 710b894351 Merge zizzer:/bk/multiarch into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch Korey Sewell 2006-02-08 16:24:25 -05:00
  • b6d21b7a34 Code for more "BasicOp" instructions ... formats for all instructions in place ... Edits to Branch Format Korey Sewell 2006-02-08 16:24:04 -05:00
  • b203d7bd33 add at least BasicOp Format to most if not all instructions and file name changes ... Korey Sewell 2006-02-08 14:50:07 -05:00
  • 524da7cd20 Replace ad-hoc or locally defined power-of-2 tests with isPowerOf2() from intmath.hh. Steve Reinhardt 2006-02-08 10:40:43 -05:00
  • f444a7e799 Moved the alpha isa_desc to conform to the new naming system. Gabe Black 2006-02-08 02:17:47 -05:00
  • e59fdcdd39 Some fixups Gabe Black 2006-02-08 01:57:47 -05:00
  • 29bc6c086a Merge gblack@m5.eecs.umich.edu:/bk/multiarch into ewok.(none):/home/gblack/m5/multiarch Gabe Black 2006-02-08 01:04:32 -05:00
  • 82f2ae56ed Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh Gabe Black 2006-02-08 01:03:55 -05:00
  • 7219693f4c Actually we do need a separate class for Integer Ops with Immediates!!! The extra class is needed because of the necessisty of an immediate member variable. Korey Sewell 2006-02-07 19:28:19 -05:00
  • d30262d480 name changes ... minor IntOP format change Korey Sewell 2006-02-07 18:36:08 -05:00
  • 3298e937d3 Merge zizzer:/z/m5/Bitkeeper/newmem into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmem2 Ron Dreslinski 2006-02-07 17:33:14 -05:00
  • eabb0cfc78 Pushing current state. Need to fix compilation problems, have moved the SCONS script to build memory objects first. Ron Dreslinski 2006-02-07 17:33:03 -05:00
  • 6d2807ded8 1st full draft switch statement actions for all integer arithmetic operations and the majority of the load & store operations (not all of FP-Ops), Korey Sewell 2006-02-04 18:59:44 -05:00
  • 035b443093 mainly added minor support for the basic arithmetic operations (add, mult, shift) Korey Sewell 2006-02-03 23:04:06 -05:00
  • 989292a0fa Update for new memory system. Uses the ports to access memory now. Also supports the response path of the new memory system, as well as retrying accesses. Kevin Lim 2006-02-03 15:21:06 -05:00
  • 4e36678028 Adding some more things toward having cpu->mem test in place. Still need to work on compilation issues. Ron Dreslinski 2006-02-03 14:54:37 -05:00
  • 1e222c1502 .h -> .def Korey Sewell 2006-02-03 03:56:57 -05:00
  • de1f3a7b6b Rename: arch/mips/isa/formats/tlb.format -> arch/mips/isa/formats/tlbop.format Korey Sewell 2006-02-03 03:39:08 -05:00
  • f7a75d872b Checkin (Merge?) files ... Added a few new format files Korey Sewell 2006-02-03 03:38:27 -05:00
  • 2939a7089a byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions. Gabe Black 2006-02-03 00:16:44 -05:00
  • 3d2773195c Merge zizzer:/bk/multiarch into zeep.eecs.umich.edu:/z/saidi/work/m5.multiarch Ali Saidi 2006-02-01 17:52:40 -05:00
  • 860273101f Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5 into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch Gabe Black 2006-02-01 17:41:03 -05:00
  • a236a3ade7 Fix a mistake, need to import SCons.Scanner Ali Saidi 2006-02-01 13:13:05 -05:00
  • 4c40848dcc Remove non-needed functions, fix return values of completion handler. Ron Dreslinski 2006-01-31 15:03:04 -05:00
  • 0d74f27313 More changes toward making simpleCpu use new port interface. Ron Dreslinski 2006-01-31 15:00:09 -05:00
  • 6c7fdb1be7 More include files, removing definition of SendResult whioch isn't needed anymore Ron Dreslinski 2006-01-31 14:42:42 -05:00
  • 2f644efafa Fixed some void functions with returns, first stab at cpu ports. Ron Dreslinski 2006-01-31 14:39:41 -05:00
  • fccd113e2f Merge zizzer:/bk/newmem into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem Ali Saidi 2006-01-31 14:20:48 -05:00
  • 4875b33467 changed sendresult -> bool,tick,void as appropriate first crack at io devices code made CpuRequest that derives from Request Ali Saidi 2006-01-31 14:20:39 -05:00
  • 95088d141f Add proper includes Ron Dreslinski 2006-01-31 14:15:33 -05:00
  • c0f012d13d Listing some of the enum structures Ron Dreslinski 2006-01-31 14:09:43 -05:00
  • 993934f4cb Add a scaner for .isa files. Ordering it turns out is rather important here, so it has to be defined before the rule to that calls isa_parser.py Ali Saidi 2006-01-31 13:52:23 -05:00