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Get ISA parser to at least include all the ISA correctly ... crashes with "None" error

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arch/mips/isa/decoder.isa:
    CondBranch format split up into Branch & BranchLikely formats
arch/mips/isa/formats.isa:
    include util.isa
arch/mips/isa/formats/branch.isa:
    erroneous 'e' at top of code
arch/mips/isa/formats/util.isa:
    util.isa

--HG--
extra : convert_revision : 4fc44a05e2838749e66cd70f210e8a718b34cbf3
This commit is contained in:
Korey Sewell
2006-02-16 02:51:04 -05:00
parent e7d16b0aef
commit 7446238118
4 changed files with 43 additions and 8 deletions
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19
arch/mips/isa/decoder.isa
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@@ -1,3 +1,5 @@
// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//
// The actual MIPS32 ISA decoder
@@ -144,10 +146,13 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode REGIMM_HI {
0x0: decode REGIMM_LO {
format CondBranch {
format Branch {
0x0: bltz({{ cond = (Rs.sw < 0); }});
0x1: bgez({{ cond = (Rs.sw >= 0); }});
}
format BranchLikely {
//MIPS obsolete instructions
0x2: bltzl({{ cond = (Rs.sw < 0); }});
0x3: bgezl({{ cond = (Rs.sw >= 0); }});
@@ -166,10 +171,12 @@ decode OPCODE_HI default Unknown::unknown() {
}
0x2: decode REGIMM_LO {
format CondBranch {
format Branch {
0x0: bltzal({{ cond = (Rs.sw < 0); }});
0x1: bgezal({{ cond = (Rs.sw >= 0); }});
}
format BranchLikely {
//MIPS obsolete instructions
0x2: bltzall({{ cond = (Rs.sw < 0); }});
0x3: bgezall({{ cond = (Rs.sw >= 0); }});
@@ -188,7 +195,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: jal(IsCall);
}
format CondBranch {
format Branch {
0x4: beq({{ cond = (Rs.sw == 0); }});
0x5: bne({{ cond = (Rs.sw != 0); }});
0x6: blez({{ cond = (Rs.sw <= 0); }});
@@ -360,14 +367,14 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode ND {
0x0: decode TF {
format CondBranch {
format Branch {
0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }});
0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }});
}
}
0x1: decode TF {
format CondBranch {
format BranchLikely {
0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }});
0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }});
}
@@ -737,7 +744,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
//MIPS obsolete instructions
format CondBranch {
format BranchLikely {
0x4: beql({{ cond = (Rs.sw == 0); }});
0x5: bnel({{ cond = (Rs.sw != 0); }});
0x6: blezl({{ cond = (Rs.sw <= 0); }});

4
arch/mips/isa/formats.isa
View File

@@ -1,5 +1,7 @@
//Include the basic format
//Templates from this format are used later
##include "m5/arch/mips/isa/formats/util.isa"
//Include the basic format
##include "m5/arch/mips/isa/formats/basic.isa"
//Include the integerOp and integerOpCc format

2
arch/mips/isa/formats/branch.isa
View File

@@ -1,4 +1,4 @@
e// -*- mode:c++ -*-
// -*- mode:c++ -*-
////////////////////////////////////////////////////////////////////
//

26
arch/mips/isa/formats/util.isa Normal file
View File

@@ -0,0 +1,26 @@
// -*- mode:c++ -*-
let {{
def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
# Declare basic control transfer w/o link (i.e. link reg is R31)
nolink_code = 'NPC = %s;\n' % npc_expr
nolink_iop = InstObjParams(name, Name, base_class,
CodeBlock(nolink_code), flags)
header_output = BasicDeclare.subst(nolink_iop)
decoder_output = BasicConstructor.subst(nolink_iop)
exec_output = BasicExecute.subst(nolink_iop)
# Generate declaration of '*AndLink' version, append to decls
link_code = 'Ra = NPC & ~3;\n' + nolink_code
link_iop = InstObjParams(name, Name + 'AndLink', base_class,
CodeBlock(link_code), flags)
header_output += BasicDeclare.subst(link_iop)
decoder_output += BasicConstructor.subst(link_iop)
exec_output += BasicExecute.subst(link_iop)
# need to use link_iop for the decode template since it is expecting
# the shorter version of class_name (w/o "AndLink")
return (header_output, decoder_output,
JumpOrBranchDecode.subst(nolink_iop), exec_output)
}};