9f90291c54
cpus: fix cpu progress event this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting progress events through repeatEvent flag and also changing the interval of the progress event as well
Korey Sewell
2009-05-05 02:39:05 -04:00
dc35d2f125
scons: re-work the *Source functions to take more information. Start by turning all of the *Source functions into classes so we can do more calculations and more easily collect the data we need. Add parameters to the new classes for indicating what sorts of flags the objects should be compiled with so we can allow certain files to be compiled without Werror for example.
Nathan Binkert
2009-05-04 16:58:24 -07:00
7146eb79f1
X86: Precompute the default and alternate address and operand size and the stack size.
Gabe Black
2009-04-26 16:49:24 -07:00
b6bfe8af26
X86: Split out the internal memory space from the regular translate() and precompute mode.
Gabe Black
2009-04-26 16:48:44 -07:00
4ee34dfb4e
X86: Centralize updates to the handy M5 reg.
Gabe Black
2009-04-26 16:47:48 -07:00
06b3e3c303
X86: Implement lowest priority interrupts more correctly. Lowest priority interrupts are now delivered based on a rotating offset into the list of potential recipients. There could be parasitic cases were a processor gets picked on and ends up at that rotating offset all the time, but it's much more likely that the group will stay consistent and the pain will be distributed evenly.
Gabe Black
2009-04-26 02:09:54 -07:00
2f34a7eaeb
X86: Tell the function that sends int messages who to send to instead of figuring it out itself.
Gabe Black
2009-04-26 02:09:27 -07:00
88ab4bb257
X86: Make the local APICs register themselves with the IO APIC. This is a hack so that the IO APIC can figure out information about the local APICs. The local APICs still have no way to find out about each other. Ideally, when the local APICs update state that's relevant to somebody else, they'd send an update to everyone. Without being able to do a broadcast, that would still require knowing who else there is to notify. Other broadcasts are implemented using assumptions that may not always be true.
Gabe Black
2009-04-26 02:09:13 -07:00
c5e2cf841d
X86: Record the initial APIC ID which identifies an APIC in M5. The ID as exposed to software can be changed. Tracking those changes in M5 would be cumbersome, especially since there's no guarantee the IDs will remain unique.
Gabe Black
2009-04-26 02:06:21 -07:00
8d84f81e70
X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment.
Gabe Black
2009-04-26 02:04:32 -07:00
9d0fa27d09
SPARC: Tighten up the clone system call and SPARCs copyRegs.
Gabe Black
2009-04-24 23:11:21 -07:00
7c056e44e5
request: reorganize flags to group related flags together.
Steve Reinhardt
2009-04-23 06:44:32 -07:00
ee7055c289
X86: Put the StoreCheck flag with the others, and don't collide with other flags.
Gabe Black
2009-04-23 01:43:00 -07:00
aa9b4e6a68
stats: Move flags into info.hh and use base/flags.hh to manage the flags
Nathan Binkert
2009-04-22 13:38:01 -07:00
8c3eb1a192
stats: Shuffle around info stuff so it can be accessed separately
Nathan Binkert
2009-04-22 13:38:00 -07:00
4d9f25b75c
stats: Rename the info classes to hopefully make things a bit clearer FooInfoBase became FooInfo FooInfo became FooInfoProxy
Nathan Binkert
2009-04-22 13:38:00 -07:00
567cab6859
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
Nathan Binkert
2009-04-22 10:25:17 -07:00
61a68371be
stats: fix initialization bug in distribution text output
Nathan Binkert
2009-04-22 06:44:29 -07:00
e7fa4f2f8e
i8254xGBe: major style overhaul. Moved DescCache template functions from .hh to .cc file. Also fixed lots of line-wrapping problems, and some irregular indentation.
Steve Reinhardt
2009-04-22 01:58:53 -04:00
7b40c36fbd
Update stats for new single bad-address responder. Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
Steve Reinhardt
2009-04-22 01:55:52 -04:00
6629d9b2bc
mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
Steve Reinhardt
2008-07-16 11:10:33 -07:00
05d8c9acb8
scons: Rename the basic environment from env -> main. env is used as a local variable all over the place and sometimes it is easy to get confused as to whether the global env or local env is being used. This will become especially important when I change the way we support our variants.
Nathan Binkert
2009-04-21 17:17:16 -07:00
56e5509bfd
scons: Fix two problems with the way that the library path is generated. 1) -L is automatically added, so don't do it ourselves 2) prepend the paths for gzstream and libelf so they are certain to come first. The problem is that python might add /usr/lib to the path and the user might have a locally installed version of libelf installed.
Nathan Binkert
2009-04-21 17:17:15 -07:00
4d001e43da
Automated merge with ssh://m5sim.org//repo/m5
Nathan Binkert
2009-04-21 16:04:55 -07:00
fcc142463d
pseudo: only include kernel stats if FULL_SYSTEM.
Nathan Binkert
2009-04-21 15:40:26 -07:00
43c7698f49
arm: include missing file for arm
Nathan Binkert
2009-04-21 15:40:26 -07:00
50f1570352
arm: Unify the ARM tlb. We forgot about this when we did the rest. This code compiles, but there are no tests still
Nathan Binkert
2009-04-21 15:40:25 -07:00
4f7d6a881c
rundiff: flush stdout after each diff
Steve Reinhardt
2009-04-21 11:34:26 -07:00
c370a9cb98
FastAlloc: track allocation tick in debug mode, minor enhancements to debug output
Steve Reinhardt
2009-01-08 14:13:33 -08:00
fff9c93568
scons: make default target work again
Nathan Binkert
2009-04-21 10:49:06 -07:00
7b2f8e6857
Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
Steve Reinhardt
2009-04-21 08:37:50 -07:00
03b3925e58
syscall_emul: style fixes (mostly wrapping overly long lines)
Steve Reinhardt
2009-04-21 08:17:36 -07:00
52b6764f31
syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.
Steve Reinhardt
2009-04-21 08:17:36 -07:00
b0e9654f86
Commit m5threads package.
Daniel Sanchez
2009-04-21 08:17:36 -07:00
b0489d18ed
SCons: Export export_vars so SConsopts files can add to them
Nathan Binkert
2009-04-21 08:17:36 -07:00
97b6947eb7
Minor tweaks for future Ruby compatibility.
Steve Reinhardt
2009-04-21 08:17:36 -07:00
eb3b6935d3
request: add PREFETCH flag.
Steve Reinhardt
2009-04-21 08:17:10 -07:00
3083268d60
request: rename INST_READ to INST_FETCH.
Steve Reinhardt
2009-04-20 18:54:02 -07:00
7f8ea68a30
request: split public and private flags into separate fields. This frees up needed space for more public flags. Also: - remove unused Request accessor methods - make Packet use public Request accessors, so it need not be a friend
Steve Reinhardt
2009-04-20 18:40:00 -07:00
9e9a34fed1
Mem: Fill out the comment that describes the LOCKED request flag.
Gabe Black
2009-04-19 22:00:24 -07:00
bd6f2bb538
Mem: Change isLlsc to isLLSC.
Gabe Black
2009-04-19 21:44:15 -07:00
089b384086
X86: Fix the functions that manipulate large bit arrays in the local APIC.
Gabe Black
2009-04-19 13:47:15 -07:00
eee74ba427
X86: Fix up a copyright.
Gabe Black
2009-04-19 13:17:35 -07:00
6910baa015
X86: Fix how the TLB handles the storecheck flag.
Gabe Black
2009-04-19 04:57:51 -07:00
0a6ff60caa
X86: Recognize and handle the lock legacy prefix.
Gabe Black
2009-04-19 04:57:28 -07:00
61edc9ba66
X86: Implement a locking version of XADD.
Gabe Black
2009-04-19 04:56:49 -07:00
209cfc89fd
X86: Implement a locking version of BTC.
Gabe Black
2009-04-19 04:56:45 -07:00
e475cf85f0
X86: Implement a locking version of BTR.
Gabe Black
2009-04-19 04:56:43 -07:00
43f58927d6
X86: Implement a locking version of CMPXCHG.
Gabe Black
2009-04-19 04:56:40 -07:00
b493906eb9
X86: Implement a locking version of BTS.
Gabe Black
2009-04-19 04:56:36 -07:00
985d959ea6
X86: Implement a locking version of DEC.
Gabe Black
2009-04-19 04:56:34 -07:00
4f2d4f466a
X86: Implement a locking version of INC.
Gabe Black
2009-04-19 04:56:31 -07:00
2394f73f90
X86: Implement a locking version of NEG.
Gabe Black
2009-04-19 04:56:28 -07:00
9b9b7a412c
X86: Implement a locking version of NOT.
Gabe Black
2009-04-19 04:56:25 -07:00
b8f81c62a2
X86: Implement a locking version of XCHG.
Gabe Black
2009-04-19 04:56:22 -07:00
750f5a0a67
X86: Implement a locking version of XOR.
Gabe Black
2009-04-19 04:56:20 -07:00
cfb289ebeb
X86: Implement a locking version of SUB.
Gabe Black
2009-04-19 04:56:16 -07:00
789b3191b9
X86: Implement a locking version of AND.
Gabe Black
2009-04-19 04:56:14 -07:00
e742cad6f4
X86: Implement a locking version of SBB.
Gabe Black
2009-04-19 04:56:11 -07:00
193265c6e5
X86: Implement a locking version of ADC.
Gabe Black
2009-04-19 04:56:08 -07:00
2f607b882c
X86: Implement a locking version of OR.
Gabe Black
2009-04-19 04:56:06 -07:00
a7f79c9049
X86: Implement a locking version of ADD.
Gabe Black
2009-04-19 04:56:02 -07:00
d90456a486
X86: Implement the stul microop. This microop does a store and unlocks the requested address. The RISC86 microop ISA doesn't seem to have an equivalent to this, so I'm guessing that the store following an ldstl is automatically unlocking. We don't do it this way for performance reasons since the behavior is the same.
Gabe Black
2009-04-19 04:55:58 -07:00
d2554ff030
X86: Implement the ldstl microop. This microop does a load, checks that a store would succeed, and locks the requested address.
Gabe Black
2009-04-19 04:55:43 -07:00
1a8a765a5c
CPUs: Make the atomic CPU support locked memory accesses.
Gabe Black
2009-04-19 04:50:07 -07:00
742c3f045e
Memory: Add a LOCKED flag back in for x86 style locking.
Gabe Black
2009-04-19 04:39:25 -07:00
3e5f487663
Memory: Rename LOCKED for load locked store conditional to LLSC.
Gabe Black
2009-04-19 04:25:01 -07:00
ca85981478
SE mode: Make keeping track of the number of syscalls less hacky.
Gabe Black
2009-04-19 04:15:32 -07:00
b8333a5155
X86: Actually put the PCI INTA entry into the MP tables.
Gabe Black
2009-04-19 04:15:18 -07:00
e174239bd8
X86: Mask the PIC at startup to avoid a glitch which causes an NMI.
Gabe Black
2009-04-19 04:15:06 -07:00
25e223c30f
X86: Make E820 report nice, round (and correct) numbers.
Gabe Black
2009-04-19 04:14:48 -07:00
5f164ba720
X86: Actually handle 16 bit mode modrm.
Gabe Black
2009-04-19 04:14:31 -07:00
93cccf7d19
X86: Make the TEST instruction set all the flags it's supposed to.
Gabe Black
2009-04-19 04:14:16 -07:00
f82c123242
X86: Implement broadcast IPIs.
Gabe Black
2009-04-19 04:14:01 -07:00
829e424353
X86: Fix the ordering of the vendor string reported by CPUID.
Gabe Black
2009-04-19 04:13:45 -07:00
8b2ac20753
X86: Keep track of what the initial count value was in the LAPIC timer.
Gabe Black
2009-04-19 03:56:57 -07:00
18b3863127
X86: Only recognize the first startup IPI after INIT or reset.
Gabe Black
2009-04-19 03:56:36 -07:00
4d32cd10ce
X86: Use recvResponse to implement the idle bit in the Local APIC ICR.
Gabe Black
2009-04-19 03:56:24 -07:00
bdda224d41
X86: Add a function which gets called when an interrupt message has been delivered.
Gabe Black
2009-04-19 03:54:11 -07:00
3031af21c7
X86: Fix the flags for interrupt response messages.
Gabe Black
2009-04-19 03:53:29 -07:00
3eed59768c
X86: Explicitly use the right width in a few places that need a 64 bit value.
Gabe Black
2009-04-19 03:47:59 -07:00
8761057c78
X86: Keep track of the pioAddr for the local APIC.
Gabe Black
2009-04-19 03:47:12 -07:00
038225a6ca
X86: Implement far jmp.
Gabe Black
2009-04-19 03:42:41 -07:00
3b1b21cb15
X86: Some segment selectors can be used when "NULL".
Gabe Black
2009-04-19 03:41:10 -07:00
a0cc081997
X86: Fix a bug in the chks microop where it ignored that it found a fault.
Gabe Black
2009-04-19 03:40:08 -07:00
f2ff5b9249
X86: Make the interrupt entering microcode record the value to use, not actually use it.
Gabe Black
2009-04-19 03:36:57 -07:00
35eea4191b
X86: LEA calculates an address before segmentation.
Gabe Black
2009-04-19 03:24:51 -07:00
bdd55ec8b6
X86: Implement the save machine status word instruction (SMSW).
Gabe Black
2009-04-19 03:22:38 -07:00
d86cd1d2a0
X86: Implement the load machine status word instruction (LMSW).
Gabe Black
2009-04-19 03:17:14 -07:00
b4ad233c0c
X86: Update the stats for the fix for CPUID.
Gabe Black
2009-04-19 03:14:33 -07:00
eba640c963
X86: Only use %eax to select a function and look like we support sse2.
Gabe Black
2009-04-19 03:11:24 -07:00
27e54982b4
X86: Fix the mov to segment selector in real mode instruction microcode.
Gabe Black
2009-04-19 03:08:40 -07:00
633c96bd85
X86: The startup IPI delivery mode is not reserved.
Gabe Black
2009-04-19 03:01:46 -07:00
08f021aad0
X86: Implement the STARTUP IPI.
Gabe Black
2009-04-19 02:56:03 -07:00
d277feb925
X86: Implement the INIT IPI.
Gabe Black
2009-04-19 02:53:00 -07:00
a340b214cf
X86: Fix the halt microop.
Gabe Black
2009-04-19 02:51:09 -07:00
641513fe08
X86: Start implementing the interrupt command register in the local APIC.
Gabe Black
2009-04-19 02:43:22 -07:00
9549694ecd
X86: Make code that sends an interrupt from the IO APIC available for IPIs.
Gabe Black
2009-04-19 02:42:19 -07:00
Korey Sewell