The sc_vector class is available through systemc.h already, so there's
no reason to include an internal path which is only there on Accellera
by coincidence of the implementation.
Change-Id: I41cab4711c0837cd9b20c21871b79be5165bf498
Reviewed-on: https://gem5-review.googlesource.com/11176
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
The only required option for the script is the path to a build
directory, for instance build/ARM. It uses that when running scons and
when referring to generated files (like the built versions of the
tests). It uses the location of the script itself to find source files,
like the "golden" version of outputs.
This script runs tests in three phases, compilation, running, and
then verification. By default, all three phases are run for all tests,
but which phases run and how they work can be customized by specifying
them explicitly on the command line with the --phase option.
Each time the --phase option shows up on the command line, it should
be followed by the name of the phase being specified. That both
declares that that phase should be run, and also that any subsequent
options apply to that phase, at least until the next --phase option.
Currently, only the "compile" and "execute" phases are implemented, and
only the "compile" phase has been tested at all or has any options
defined. The "compile" phase simply takes all the options it was given
and pass them on to scons. The "verify" phase simply prints a message
which says what it would have verified.
The script can list the available tests with the --list option, as
determined by the json systemc test manifest file which scons can
generate, and which the script can refresh if passed the --update-json
option. You can also specify what "flavor" of build you want to do, ie
opt, debug, fast, etc., with the --flavor option. Only one flavor can
be tested at a time, but that should be the desired behavior most of
the time. If multiple flavors need to be tested, the script can be
invoked multiple times.
Finally, there is a --filter option which accepts a python expression
as a string. That expression is evaluated in the namespace of the
properties of each test in the json file, and if it returns true then
that test is run. For instance, to verify only compile_only tests, you
would use:
systemc/tests/verify.py build/ARM --filter 'compile_only'
To test only compile_only tests named bob, you would run this:
systemc/tests/verify.py build/ARM --filter \
'compile_only && name ="bob"'
Also included is a simple config.py which is the beginning of a config
which will run the systemc regression tests. Right now, all it knows
how to do is run sc_main.
Change-Id: I62666be8b1622d1355153e623b4274a939507e44
Reviewed-on: https://gem5-review.googlesource.com/10975
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Otherwise, having hundreds of statically linked gem5s takes up a huge
amount of space, and all those repeated linkings brings the mightiest
workstation to its knees with sufficient parallelism, or will take
forever without it.
Change-Id: I4c358b1a50c5e2b0027ac72423f887e24c786b19
Reviewed-on: https://gem5-review.googlesource.com/10959
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
The standard says there's not supposed to be a default writer policy
for the sc_buffer template class, but in the Accellera implementation
there is, and the regression tests depend on it to compile.
Change-Id: I31d17617441224e86c56c54e45364be8f4f45b00
Reviewed-on: https://gem5-review.googlesource.com/10957
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This mechanism scans the systemc test directories as described in their
original distribution. It tells scons how to build each test
executable, and also how to build a json manifest file which
lists all the tests and some properties about them.
Change-Id: I8ebc748c1aed71f0bb76e04a2040f15abd2837d9
Reviewed-on: https://gem5-review.googlesource.com/10956
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
The regression tests use this function. In the Accellera implementation
it seems to just do some error checking, so our version doesn't do
anything for now.
Change-Id: Icaad45e934bad69e301bc0234f73e69791940736
Reviewed-on: https://gem5-review.googlesource.com/10854
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
The fiber will run until either sc_main returns, or until sc_start is
called. If sc_start is called, then the fiber will only be paused and
waiting for simulation cycles to be run by gem5. Once sc_pause and
sc_stop are implemented, if those are called the sc_main fiber will
be re-entered and allowed to run further towards completion.
Change-Id: I4df94f4f6fed8d49471732619a203d734d9a13a6
Reviewed-on: https://gem5-review.googlesource.com/10849
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Previously, reg_class_impl.hh was added in order to prevent a cyclic
dependency between it and the_isa.hh (See
http://reviews.gem5.org/r/3754). It was determined that this was not
necessary. The two files had almost entirely the same includes, and the
current test-suite including multiple gcc and clang compilers on both
MacOS and Linux successfully built the library with all functionality
moved into the reg_class.hh file.
Change-Id: I0319e187b9eb280726a003951bb1ce315ffe17f5
Signed-off-by: Bradley Wang <radwang@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/11869
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Please note that at the moment these instructions behave like the
existing load-acquire instructions, which follow the more conservative
RCsc consistency model. This means that the new instructions are
_functionally_ correct, but the potential performance improvements
enabled by the RCpc model will not be experienced in timing
simulations.
Change-Id: I04c786ad2941072bf28feba7d2ec6e142c8b74cb
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11989
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
These are the headers originally written by Accellera with a few
modifications. Most significantly, I went through and mostly (but not
entirely) manually editted them to conform to gem5 style and to be
more self consistent. Second, I resolved some macros which optionally
select features. I removed support for deprecated functions, and
otherwise enabled everything.
The actual implementation behind these headers will also be ported
over, but in a subsequent change.
Change-Id: I203d3f6c8a3af9120b946001d01defbb0643a6b6
Reviewed-on: https://gem5-review.googlesource.com/10843
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This patch adds the uret, sret, and mret instructions for use with
returning from user-, supervisor-, and machine-level code, respectively.
These instructions read the STATUS register to determine the previous
privilege level and modify it to re-enable interrupts at the old
privilege level. These instructions can only be executed at the
corresponding privilege level or higher.
Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9
Reviewed-on: https://gem5-review.googlesource.com/11136
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Robert Scheffel <robert.scheffel1@tu-dresden.de>
RISC-V has a set of CSRs that contain information about a trap that was
taken into each privilegel level, such as illegal instruction bytes or
faulting address. This patch adds that register, modifies existing
faults to make use of it, and adds a new fault for future use with
handling page faults and bad addresses.
Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551
Reviewed-on: https://gem5-review.googlesource.com/11135
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
This patch adds support for handling RISC-V faults, including tracking
current and previous execution privilege, correctly switching to
the privilege mode specified by CSRs, and setting/storing the PC. It
also includes changes introduced by patch #9821, which disables
interrupts during handling of a fault.
Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9
Reviewed-on: https://gem5-review.googlesource.com/9161
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
ucontext functions (like getcontext, setcontext etc) have been marked
as deprecated and are hence hidden in latest macOS releases.
This patch uncovers them; warnings wil be produced but compilation
won't fail since -Wno-error=deprecated-declarations flag is currently
used.
Change-Id: Ic10e6f77a38875828b1891eaed2f0626ecffff67
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11729
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This patch allows to instantiate a Traffic generator starting from a
generic SimObject, so that linking to a BaseTrafficGen only is no longer
mandatory. This permits SimObjects different than a BaseTrafficGen to
instantiate generators and to manually specify the MasterID they
will be using when generating memory requests.
Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11789
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This change is because I want to make CacheBlk::data private, so that
I can track all the places which write to it. But to keep that commit
smaller (it is pretty big, because of all the places which might
change it), I have split this into a commit of its own.
Change-Id: I15a2fc1752085ff3681f5c74ec90be3828a559ea
Reviewed-on: https://gem5-review.googlesource.com/11829
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
These are the header files as defined by the standard, although some
predefined channel types and most of the sc_dt namespace have yet to be
stubbed out, and so those portions are excluded.
Change-Id: Ic70f887c06e591974a4265c820eb0fdfa740d19a
Reviewed-on: https://gem5-review.googlesource.com/10838
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Most (but not all) of the SystemC headers are part of the "external"
interface that an existing, standard compliant module would include
through <systemc.h> or <systemc>. Since those follow slightly different
rules (relative includes, no gem5 includes), this change separates them
out so that they're easier to identify.
Also, this change moves the other files into a "core" subdirectory,
with the intention to add a "dt", aka data type, directory some time in
the future when those standard defined types are implemented.
Change-Id: Ida63f9cc0bc0431024d4dd691cc5b22b944a99a8
Reviewed-on: https://gem5-review.googlesource.com/10835
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Free the squahsed instructions' heads of DepGraph in IQ squashing
In a system with large register file (ex.2048), the number of
DynInst hits the hardcoded limit (1500). This is caused by
missing freeing the heads of DepGraph in IQ. IQ only clears
out the heads when instructions reach writeback stage.
If a instruction is squashed before writeback stage, its head of
dependency graph, which holds the instruction's DynInstPtr,
would not be cleared out. This prevents freeing the DynInst of the
squahsed instruction even after it is committed.
Change-Id: I05b3db93cb6ad8960183d7ae765149c7f292e5b3
Reviewed-on: https://gem5-review.googlesource.com/7481
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
sc_main is exported as a python method on the SystemC_Kernel class and
takes a series of string arguments. The internal c++ implementation
converts those arguments into the standard argc and argv and uses them
to call the standard SystemC version of that function.
A weak SystemC version of sc_main is provided so that systemc will
compile with or without a simulation provided version of that
function. The weak version just complains and dies.
Change-Id: Iad735536c37c8bc85d06cf24779f607ae4309b8b
Reviewed-on: https://gem5-review.googlesource.com/10824
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
This class is mostly implemented as defined by the spec, except that
it doesn't maintain the module name stack (which doesn't yet exist).
Change-Id: I05fdc4aa40fb0497b0165824baee87ebf01a7821
Reviewed-on: https://gem5-review.googlesource.com/10823
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are
- Bridge::BridgeMasterPort::checkFunctional
- calls Packet::checkFunctional
- MSHR::checkFunctional
- calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
- calls Packet::checkFunctional
- Queue<>::checkFunctional
(of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
- Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
- calls Packet::checkFunctional
- WriteQueueEntry::TargetList
- calls Packet::checkFunctional
- MemDelay::checkFunctional
- calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
- calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
- calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
- calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
- calls Packet::doFunctional
Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
To avoid unintentional variable capture, all std calls must be
prefixed. These are the identifiers which are in the std
namespace (according to
https://en.cppreference.com/w/cpp/symbol_index), but that will remain
unprefixed with this change:
int8_t int16_t int32_t int64_t
uint8_t uint16_t uint32_t uint64_t
The (u)int types are included from the packet header file, which
includes <inttypes.h>, where they occur in the global namespace. They
are in the std namespace in <cinttypes>/<cstdint>.
There is an occurrence of "set" in this file, which is "Packet::set"
and not "std::set", so it is not prefixed with the std namespace
Change-Id: I7f6c0b61b09658e224fe31a9f73150b81861d6f8
Reviewed-on: https://gem5-review.googlesource.com/11809
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
