Commit Graph

13 Commits

Author SHA1 Message Date
Daniel R. Carvalho
4b2118ed4b misc: Remove sim/cur_tick dependency from sim/core.hh
Remove this unnecessary dependency. Fixed all incorrect
includes of sim/core.hh.

Change-Id: I3ae282dbaeb45fbf4630237a3ab9b1a593ffbe0c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43592
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-06 09:59:11 +00:00
Daniel R. Carvalho
974a47dfb9 misc: Adopt the gem5 namespace
Apply the gem5 namespace to the codebase.

Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.

A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.

std out should not be included in the gem5 namespace, so
they weren't.

ProtoMessage has not been included in the gem5 namespace,
since I'm not familiar with how proto works.

Regarding the SystemC files, although they belong to gem5,
they actually perform integration between gem5 and SystemC;
therefore, it deserved its own separate namespace.

Files that are automatically generated have been included
in the gem5 namespace.

The .isa files currently are limited to a single namespace.
This limitation should be later removed to make it easier
to accomodate a better API.

Regarding the files in util, gem5:: was prepended where
suitable. Notice that this patch was tested as much as
possible given that most of these were already not
previously compiling.

Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-01 19:08:24 +00:00
Tom Rollet
15cba2ad1c mem-cache: Queue,QueueEntry, NSHR::TargetList inherit from Named
With this change, when using a DPRINTF statment on a class inheriting
from the Queue or QueueEntry class, the name at the start of the log
line will be meaningful.

Currently affected classes:
    MSHRqueue
    MSHR
    MSHR::TargetList
    WriteQueue
    WriteQueueEntry

Change-Id: I4e5ac080fec572961f9f1d9f88429ed6e72d8994
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-29 07:06:18 +00:00
Daniel R. Carvalho
469f0671d1 misc: Fix coding style for class-opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *class [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>class X ... {

by:

<indent level>class X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^class ([A-Za-z].*) \{$/class \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    class ([A-Za-z].*) \{$/    class \1\n    \{/g'

and so on.

Change-Id: I17615ce16a333d69867b27c7bae0f4fdafd8b2eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39015
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Gabe Black
921a72f4f3 mem: Delete authors lists from mem files.
Change-Id: I439d64d01950463747446a8177086eb276b8db55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25443
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-02-17 21:51:08 +00:00
Andrea Mondelli
57667bad9f cpu,mem: missing override specifier
Change-Id: I731d3ef021596450ac307461f215760a148bb28a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18348
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-24 13:43:23 +00:00
Daniel R. Carvalho
2d84dc46ba mem-cache: Add match functions to QueueEntry
Having the caller decide the matching logic is error-prone, and
frequently ends up with the secure bit being forgotten. This
change adds matching functions to the QueueEntry to avoid this
problem.

As a side effect the signature of findPending has been changed.

Change-Id: I6e494a821c1e6e841ab103ec69632c0e1b269a08
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17530
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19 16:34:00 +00:00
Daniel R. Carvalho
9f32d74db8 mem-cache: Move Target to QueueEntry
WriteQueueEntry's target has 100% functionality overlap with MSHR's,
therefore make it base to MSHR::Target.

Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-04-19 16:34:00 +00:00
Robert Kovacsics
2f17062dd9 mem: Rename Packet::checkFunctional to trySatisfyFunctional
Packet::checkFunctional also wrote data to/from the packet depending
on if it was read/write, respectively, which the 'check' in the name
would suggest otherwise. This renames it to doFunctional, which is
more suggestive. It also renames any function called checkFunctional
which calls Packet::checkFunctional. These are

- Bridge::BridgeMasterPort::checkFunctional
  - calls Packet::checkFunctional
- MSHR::checkFunctional
  - calls Packet::checkFunctional
- MSHR::TargetList::checkFunctional
  - calls Packet::checkFunctional
- Queue<>::checkFunctional
  (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h)
  - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR>
- WriteQueueEntry
  - calls Packet::checkFunctional
- WriteQueueEntry::TargetList
  - calls Packet::checkFunctional
- MemDelay::checkFunctional
  - calls QueuedSlavePort/QueuedMasterPort::checkFunctional
- Packet::checkFunctional
- PacketQueue::checkFunctional
  - calls Packet::checkFunctional
- QueuedSlavePort::checkFunctional
  - calls PacketQueue::doFunctional
- QueuedMasterPort::checkFunctional
  - calls PacketQueue::doFunctional
- SerialLink::SerialLinkMasterPort::checkFunctional
  - calls Packet::doFunctional

Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5
Reviewed-on: https://gem5-review.googlesource.com/11810
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-23 11:57:50 +00:00
Nikos Nikoleris
56865ad115 mem-cache: Fix include directives in the cache related classes
Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-31 17:45:23 +00:00
Nikos Nikoleris
41db9b95aa mem-cache: Adopt a more sensible cache class hierarchy
This patch changes what goes into the BaseCache and what goes into the
Cache, to make it easier to add a NoncoherentCache with as much re-use
as possible. A number of redundant members and definitions are also
removed in the process.

This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>

Change-Id: Ie9dd73c4ec07732e778e7416b712dad8b4bd5d4b
Reviewed-on: https://gem5-review.googlesource.com/10431
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-31 15:12:04 +00:00
Andreas Hansson
13b9d4215d mem: Deallocate all write-queue entries when sent
This patch removes the write-queue entry tracking previously used for
uncacheable writes. The write-queue entry is now deallocated as soon
as the packet is sent. As a result we also forego the stats for
uncacheable writes. Additionally, there is no longer a need to attach
the write-queue entry to the packet.
2016-04-21 04:48:07 -04:00
Andreas Hansson
041ea8107e mem: Create a separate class for the cache write buffer
This patch breaks out the cache write buffer into a separate class,
without affecting any stats. The goal of the patch is to avoid
encumbering the much-simpler write queue with the complex MSHR
handling. In a follow on patch this simplification allows us to
implement write combining.

The WriteQueue gets its own class, but shares a common ancestor, the
generic Queue, with the MSHRQueue.
2016-03-17 09:51:18 -04:00