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mem-cache: Adopt a more sensible cache class hierarchy

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This patch changes what goes into the BaseCache and what goes into the
Cache, to make it easier to add a NoncoherentCache with as much re-use
as possible. A number of redundant members and definitions are also
removed in the process.

This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>

Change-Id: Ie9dd73c4ec07732e778e7416b712dad8b4bd5d4b
Reviewed-on: https://gem5-review.googlesource.com/10431
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
This commit is contained in:
Nikos Nikoleris
2018-02-02 17:34:40 +00:00
parent d5c4dd986a
commit 41db9b95aa
10 changed files with 2293 additions and 2158 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
src/mem/cache/Cache.py vendored
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@@ -46,6 +46,12 @@ from Prefetcher import BasePrefetcher
from ReplacementPolicies import *
from Tags import *
# Enum for cache clusivity, currently mostly inclusive or mostly
# exclusive.
class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
class BaseCache(MemObject):
type = 'BaseCache'
abstract = True
@@ -90,13 +96,13 @@ class BaseCache(MemObject):
system = Param.System(Parent.any, "System we belong to")
# Enum for cache clusivity, currently mostly inclusive or mostly
# exclusive.
class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
class Cache(BaseCache):
type = 'Cache'
cxx_header = 'mem/cache/cache.hh'
# Determine if this cache sends out writebacks for clean lines, or
# simply clean evicts. In cases where a downstream cache is mostly
# exclusive with respect to this cache (acting as a victim cache),
# the clean writebacks are essential for performance. In general
# this should be set to True for anything but the last-level
# cache.
writeback_clean = Param.Bool(False, "Writeback clean lines")
# Control whether this cache should be mostly inclusive or mostly
# exclusive with respect to upstream caches. The behaviour on a
@@ -110,10 +116,7 @@ class Cache(BaseCache):
clusivity = Param.Clusivity('mostly_incl',
"Clusivity with upstream cache")
# Determine if this cache sends out writebacks for clean lines, or
# simply clean evicts. In cases where a downstream cache is mostly
# exclusive with respect to this cache (acting as a victim cache),
# the clean writebacks are essential for performance. In general
# this should be set to True for anything but the last-level
# cache.
writeback_clean = Param.Bool(False, "Writeback clean lines")
class Cache(BaseCache):
type = 'Cache'
cxx_header = 'mem/cache/cache.hh'

1543
src/mem/cache/base.cc vendored
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661
src/mem/cache/base.hh vendored
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2013, 2015-2016 ARM Limited
* Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -40,6 +40,8 @@
* Authors: Erik Hallnor
* Steve Reinhardt
* Ron Dreslinski
* Andreas Hansson
* Nikos Nikoleris
*/
/**
@@ -50,29 +52,40 @@
#ifndef __MEM_CACHE_BASE_HH__
#define __MEM_CACHE_BASE_HH__
#include <algorithm>
#include <list>
#include <cassert>
#include <cstdint>
#include <string>
#include <vector>
#include "base/logging.hh"
#include "base/addr_range.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
#include "debug/CachePort.hh"
#include "enums/Clusivity.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr_queue.hh"
#include "mem/cache/tags/base.hh"
#include "mem/cache/write_queue.hh"
#include "mem/cache/write_queue_entry.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/packet_queue.hh"
#include "mem/qport.hh"
#include "mem/request.hh"
#include "params/BaseCache.hh"
#include "sim/eventq.hh"
#include "sim/full_system.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
class BaseMasterPort;
class BasePrefetcher;
class BaseSlavePort;
class MSHR;
class MasterPort;
class QueueEntry;
struct BaseCacheParams;
/**
* A basic cache interface. Implements some common functions for speed.
*/
@@ -140,6 +153,87 @@ class BaseCache : public MemObject
virtual bool isSnooping() const { return true; }
};
/**
* Override the default behaviour of sendDeferredPacket to enable
* the memory-side cache port to also send requests based on the
* current MSHR status. This queue has a pointer to our specific
* cache implementation and is used by the MemSidePort.
*/
class CacheReqPacketQueue : public ReqPacketQueue
{
protected:
BaseCache &cache;
SnoopRespPacketQueue &snoopRespQueue;
public:
CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
SnoopRespPacketQueue &snoop_resp_queue,
const std::string &label) :
ReqPacketQueue(cache, port, label), cache(cache),
snoopRespQueue(snoop_resp_queue) { }
/**
* Override the normal sendDeferredPacket and do not only
* consider the transmit list (used for responses), but also
* requests.
*/
virtual void sendDeferredPacket();
/**
* Check if there is a conflicting snoop response about to be
* send out, and if so simply stall any requests, and schedule
* a send event at the same time as the next snoop response is
* being sent out.
*/
bool checkConflictingSnoop(Addr addr)
{
if (snoopRespQueue.hasAddr(addr)) {
DPRINTF(CachePort, "Waiting for snoop response to be "
"sent\n");
Tick when = snoopRespQueue.deferredPacketReadyTime();
schedSendEvent(when);
return true;
}
return false;
}
};
/**
* The memory-side port extends the base cache master port with
* access functions for functional, atomic and timing snoops.
*/
class MemSidePort : public CacheMasterPort
{
private:
/** The cache-specific queue. */
CacheReqPacketQueue _reqQueue;
SnoopRespPacketQueue _snoopRespQueue;
// a pointer to our specific cache implementation
BaseCache *cache;
protected:
virtual void recvTimingSnoopReq(PacketPtr pkt);
virtual bool recvTimingResp(PacketPtr pkt);
virtual Tick recvAtomicSnoop(PacketPtr pkt);
virtual void recvFunctionalSnoop(PacketPtr pkt);
public:
MemSidePort(const std::string &_name, BaseCache *_cache,
const std::string &_label);
};
/**
* A cache slave port is used for the CPU-side port of the cache,
* and it is basically a simple timing port that uses a transmit
@@ -181,8 +275,39 @@ class BaseCache : public MemObject
};
CacheSlavePort *cpuSidePort;
CacheMasterPort *memSidePort;
/**
* The CPU-side port extends the base cache slave port with access
* functions for functional, atomic and timing requests.
*/
class CpuSidePort : public CacheSlavePort
{
private:
// a pointer to our specific cache implementation
BaseCache *cache;
protected:
virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
virtual bool tryTiming(PacketPtr pkt) override;
virtual bool recvTimingReq(PacketPtr pkt) override;
virtual Tick recvAtomic(PacketPtr pkt) override;
virtual void recvFunctional(PacketPtr pkt) override;
virtual AddrRangeList getAddrRanges() const override;
public:
CpuSidePort(const std::string &_name, BaseCache *_cache,
const std::string &_label);
};
CpuSidePort cpuSidePort;
MemSidePort memSidePort;
protected:
@@ -192,6 +317,31 @@ class BaseCache : public MemObject
/** Write/writeback buffer */
WriteQueue writeBuffer;
/** Tag and data Storage */
BaseTags *tags;
/** Prefetcher */
BasePrefetcher *prefetcher;
/**
* Notify the prefetcher on every access, not just misses.
*/
const bool prefetchOnAccess;
/**
* Temporary cache block for occasional transitory use. We use
* the tempBlock to fill when allocation fails (e.g., when there
* is an outstanding request that accesses the victim block) or
* when we want to avoid allocation (e.g., exclusive caches)
*/
CacheBlk *tempBlock;
/**
* Upstream caches need this packet until true is returned, so
* hold it for deletion until a subsequent call
*/
std::unique_ptr<Packet> pendingDelete;
/**
* Mark a request as in service (sent downstream in the memory
* system), effectively making this MSHR the ordering point.
@@ -217,18 +367,349 @@ class BaseCache : public MemObject
}
/**
* Determine if we should allocate on a fill or not.
* Determine whether we should allocate on a fill or not. If this
* cache is mostly inclusive with regards to the upstream cache(s)
* we always allocate (for any non-forwarded and cacheable
* requests). In the case of a mostly exclusive cache, we allocate
* on fill if the packet did not come from a cache, thus if we:
* are dealing with a whole-line write (the latter behaves much
* like a writeback), the original target packet came from a
* non-caching source, or if we are performing a prefetch or LLSC.
*
* @param cmd Packet command being added as an MSHR target
*
* @return Whether we should allocate on a fill or not
* @param cmd Command of the incoming requesting packet
* @return Whether we should allocate on the fill
*/
virtual bool allocOnFill(MemCmd cmd) const = 0;
inline bool allocOnFill(MemCmd cmd) const
{
return clusivity == Enums::mostly_incl ||
cmd == MemCmd::WriteLineReq ||
cmd == MemCmd::ReadReq ||
cmd == MemCmd::WriteReq ||
cmd.isPrefetch() ||
cmd.isLLSC();
}
/**
* Does all the processing necessary to perform the provided request.
* @param pkt The memory request to perform.
* @param blk The cache block to be updated.
* @param lat The latency of the access.
* @param writebacks List for any writebacks that need to be performed.
* @return Boolean indicating whether the request was satisfied.
*/
virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
PacketList &writebacks);
/*
* Handle a timing request that hit in the cache
*
* @param ptk The request packet
* @param blk The referenced block
* @param request_time The tick at which the block lookup is compete
*/
virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
Tick request_time);
/*
* Handle a timing request that missed in the cache
*
* Implementation specific handling for different cache
* implementations
*
* @param ptk The request packet
* @param blk The referenced block
* @param forward_time The tick at which we can process dependent requests
* @param request_time The tick at which the block lookup is compete
*/
virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
Tick forward_time,
Tick request_time) = 0;
/*
* Handle a timing request that missed in the cache
*
* Common functionality across different cache implementations
*
* @param ptk The request packet
* @param blk The referenced block
* @param mshr Any existing mshr for the referenced cache block
* @param forward_time The tick at which we can process dependent requests
* @param request_time The tick at which the block lookup is compete
*/
void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
Tick forward_time, Tick request_time);
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
*/
virtual void recvTimingReq(PacketPtr pkt);
/**
* Handling the special case of uncacheable write responses to
* make recvTimingResp less cluttered.
*/
void handleUncacheableWriteResp(PacketPtr pkt);
/**
* Service non-deferred MSHR targets using the received response
*
* Iterates through the list of targets that can be serviced with
* the current response. Any writebacks that need to performed
* must be appended to the writebacks parameter.
*
* @param mshr The MSHR that corresponds to the reponse
* @param pkt The response packet
* @param blk The reference block
* @param writebacks List of writebacks that need to be performed
*/
virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
CacheBlk *blk, PacketList& writebacks) = 0;
/**
* Handles a response (cache line fill/write ack) from the bus.
* @param pkt The response packet
*/
virtual void recvTimingResp(PacketPtr pkt);
/**
* Snoops bus transactions to maintain coherence.
* @param pkt The current bus transaction.
*/
virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
/**
* Handle a snoop response.
* @param pkt Snoop response packet
*/
virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
/**
* Handle a request in atomic mode that missed in this cache
*
* Creates a downstream request, sends it to the memory below and
* handles the response. As we are in atomic mode all operations
* are performed immediately.
*
* @param pkt The packet with the requests
* @param blk The referenced block
* @param writebacks A list with packets for any performed writebacks
* @return Cycles for handling the request
*/
virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
PacketList &writebacks) = 0;
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
* @return The number of ticks required for the access.
*/
virtual Tick recvAtomic(PacketPtr pkt);
/**
* Snoop for the provided request in the cache and return the estimated
* time taken.
* @param pkt The memory request to snoop
* @return The number of ticks required for the snoop.
*/
virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
/**
* Performs the access specified by the request.
*
* @param pkt The request to perform.
* @param fromCpuSide from the CPU side port or the memory side port
*/
virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
/**
* Handle doing the Compare and Swap function for SPARC.
*/
void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
/**
* Return the next queue entry to service, either a pending miss
* from the MSHR queue, a buffered write from the write buffer, or
* something from the prefetcher. This function is responsible
* for prioritizing among those sources on the fly.
*/
QueueEntry* getNextQueueEntry();
/**
* Insert writebacks into the write buffer
*/
virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;
/**
* Send writebacks down the memory hierarchy in atomic mode
*/
virtual void doWritebacksAtomic(PacketList& writebacks) = 0;
/**
* Create an appropriate downstream bus request packet.
*
* Creates a new packet with the request to be send to the memory
* below, or nullptr if the current request in cpu_pkt should just
* be forwarded on.
*
* @param cpu_pkt The miss packet that needs to be satisfied.
* @param blk The referenced block, can be nullptr.
* @param needs_writable Indicates that the block must be writable
* even if the request in cpu_pkt doesn't indicate that.
* @return A packet send to the memory below
*/
virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
bool needs_writable) const = 0;
/**
* Determine if clean lines should be written back or not. In
* cases where a downstream cache is mostly inclusive we likely
* want it to act as a victim cache also for lines that have not
* been modified. Hence, we cannot simply drop the line (or send a
* clean evict), but rather need to send the actual data.
*/
const bool writebackClean;
/**
* Writebacks from the tempBlock, resulting on the response path
* in atomic mode, must happen after the call to recvAtomic has
* finished (for the right ordering of the packets). We therefore
* need to hold on to the packets, and have a method and an event
* to send them.
*/
PacketPtr tempBlockWriteback;
/**
* Send the outstanding tempBlock writeback. To be called after
* recvAtomic finishes in cases where the block we filled is in
* fact the tempBlock, and now needs to be written back.
*/
void writebackTempBlockAtomic() {
assert(tempBlockWriteback != nullptr);
PacketList writebacks{tempBlockWriteback};
doWritebacksAtomic(writebacks);
tempBlockWriteback = nullptr;
}
/**
* An event to writeback the tempBlock after recvAtomic
* finishes. To avoid other calls to recvAtomic getting in
* between, we create this event with a higher priority.
*/
EventFunctionWrapper writebackTempBlockAtomicEvent;
/**
* Perform any necessary updates to the block and perform any data
* exchange between the packet and the block. The flags of the
* packet are also set accordingly.
*
* @param pkt Request packet from upstream that hit a block
* @param blk Cache block that the packet hit
* @param deferred_response Whether this request originally missed
* @param pending_downgrade Whether the writable flag is to be removed
*/
virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
bool deferred_response = false,
bool pending_downgrade = false);
/**
* Maintain the clusivity of this cache by potentially
* invalidating a block. This method works in conjunction with
* satisfyRequest, but is separate to allow us to handle all MSHR
* targets before potentially dropping a block.
*
* @param from_cache Whether we have dealt with a packet from a cache
* @param blk The block that should potentially be dropped
*/
void maintainClusivity(bool from_cache, CacheBlk *blk);
/**
* Handle a fill operation caused by a received packet.
*
* Populates a cache block and handles all outstanding requests for the
* satisfied fill request. This version takes two memory requests. One
* contains the fill data, the other is an optional target to satisfy.
* Note that the reason we return a list of writebacks rather than
* inserting them directly in the write buffer is that this function
* is called by both atomic and timing-mode accesses, and in atomic
* mode we don't mess with the write buffer (we just perform the
* writebacks atomically once the original request is complete).
*
* @param pkt The memory request with the fill data.
* @param blk The cache block if it already exists.
* @param writebacks List for any writebacks that need to be performed.
* @param allocate Whether to allocate a block or use the temp block
* @return Pointer to the new cache block.
*/
CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
PacketList &writebacks, bool allocate);
/**
* Allocate a new block and perform any necessary writebacks
*
* Find a victim block and if necessary prepare writebacks for any
* existing data. May return nullptr if there are no replaceable
* blocks.
*
* @param addr Physical address of the new block
* @param is_secure Set if the block should be secure
* @param writebacks A list of writeback packets for the evicted blocks
* @return the allocated block
*/
CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
/**
* Evict a cache block.
*
* Performs a writeback if necesssary and invalidates the block
*
* @param blk Block to invalidate
* @return A packet with the writeback, can be nullptr
*/
M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0;
/**
* Evict a cache block.
*
* Performs a writeback if necesssary and invalidates the block
*
* @param blk Block to invalidate
* @param writebacks Return a list of packets with writebacks
*/
virtual void evictBlock(CacheBlk *blk, PacketList &writebacks) = 0;
/**
* Invalidate a cache block.
*
* @param blk Block to invalidate
*/
void invalidateBlock(CacheBlk *blk);
/**
* Create a writeback request for the given block.
*
* @param blk The block to writeback.
* @return The writeback request for the block.
*/
PacketPtr writebackBlk(CacheBlk *blk);
/**
* Create a writeclean request for the given block.
*
* Creates a request that writes the block to the cache below
* without evicting the block from the current cache.
*
* @param blk The block to write clean.
* @param dest The destination of the write clean operation.
* @param id Use the given packet id for the write clean operation.
* @return The generated write clean packet.
*/
PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);
/**
* Write back dirty blocks in the cache using functional accesses.
*/
virtual void memWriteback() override = 0;
virtual void memWriteback() override;
/**
* Invalidates all blocks in the cache.
*
@@ -236,13 +717,14 @@ class BaseCache : public MemObject
* memory. Make sure to call functionalWriteback() first if you
* want the to write them to memory.
*/
virtual void memInvalidate() override = 0;
virtual void memInvalidate() override;
/**
* Determine if there are any dirty blocks in the cache.
*
* \return true if at least one block is dirty, false otherwise.
* @return true if at least one block is dirty, false otherwise.
*/
virtual bool isDirty() const = 0;
bool isDirty() const;
/**
* Determine if an address is in the ranges covered by this
@@ -254,6 +736,11 @@ class BaseCache : public MemObject
*/
bool inRange(Addr addr) const;
/**
* Find next request ready time from among possible sources.
*/
Tick nextQueueReadyTime() const;
/** Block size of this cache */
const unsigned blkSize;
@@ -292,6 +779,13 @@ class BaseCache : public MemObject
/** Do we forward snoops from mem side port through to cpu side port? */
bool forwardSnoops;
/**
* Clusivity with respect to the upstream cache, determining if we
* fill into both this cache and the cache above on a miss. Note
* that we currently do not support strict clusivity policies.
*/
const Enums::Clusivity clusivity;
/**
* Is this cache read only, for example the instruction cache, or
* table-walker cache. A cache that is read only should never see
@@ -463,18 +957,18 @@ class BaseCache : public MemObject
/**
* Register stats for this object.
*/
virtual void regStats() override;
void regStats() override;
public:
BaseCache(const BaseCacheParams *p, unsigned blk_size);
~BaseCache() {}
~BaseCache();
virtual void init() override;
void init() override;
virtual BaseMasterPort &getMasterPort(const std::string &if_name,
PortID idx = InvalidPortID) override;
virtual BaseSlavePort &getSlavePort(const std::string &if_name,
PortID idx = InvalidPortID) override;
BaseMasterPort &getMasterPort(const std::string &if_name,
PortID idx = InvalidPortID) override;
BaseSlavePort &getSlavePort(const std::string &if_name,
PortID idx = InvalidPortID) override;
/**
* Query block size of a cache.
@@ -548,7 +1042,7 @@ class BaseCache : public MemObject
if (blocked == 0) {
blocked_causes[cause]++;
blockedCycle = curCycle();
cpuSidePort->setBlocked();
cpuSidePort.setBlocked();
}
blocked |= flag;
DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
@@ -568,7 +1062,7 @@ class BaseCache : public MemObject
DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
if (blocked == 0) {
blocked_cycles[cause] += curCycle() - blockedCycle;
cpuSidePort->clearBlocked();
cpuSidePort.clearBlocked();
}
}
@@ -582,12 +1076,16 @@ class BaseCache : public MemObject
*/
void schedMemSideSendEvent(Tick time)
{
memSidePort->schedSendEvent(time);
memSidePort.schedSendEvent(time);
}
virtual bool inCache(Addr addr, bool is_secure) const = 0;
bool inCache(Addr addr, bool is_secure) const {
return tags->findBlock(addr, is_secure);
}
virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
bool inMissQueue(Addr addr, bool is_secure) const {
return mshrQueue.findMatch(addr, is_secure);
}
void incMissCount(PacketPtr pkt)
{
@@ -607,6 +1105,109 @@ class BaseCache : public MemObject
}
/**
* Cache block visitor that writes back dirty cache blocks using
* functional writes.
*
* @return Always returns true.
*/
bool writebackVisitor(CacheBlk &blk);
/**
* Cache block visitor that invalidates all blocks in the cache.
*
* @warn Dirty cache lines will not be written back to memory.
*
* @return Always returns true.
*/
bool invalidateVisitor(CacheBlk &blk);
/**
* Take an MSHR, turn it into a suitable downstream packet, and
* send it out. This construct allows a queue entry to choose a suitable
* approach based on its type.
*
* @param mshr The MSHR to turn into a packet and send
* @return True if the port is waiting for a retry
*/
virtual bool sendMSHRQueuePacket(MSHR* mshr);
/**
* Similar to sendMSHR, but for a write-queue entry
* instead. Create the packet, and send it, and if successful also
* mark the entry in service.
*
* @param wq_entry The write-queue entry to turn into a packet and send
* @return True if the port is waiting for a retry
*/
bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
/**
* Serialize the state of the caches
*
* We currently don't support checkpointing cache state, so this panics.
*/
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
/**
* Wrap a method and present it as a cache block visitor.
*
* For example the forEachBlk method in the tag arrays expects a
* callable object/function as their parameter. This class wraps a
* method in an object and presents callable object that adheres to
* the cache block visitor protocol.
*/
class CacheBlkVisitorWrapper : public CacheBlkVisitor
{
public:
typedef bool (BaseCache::*VisitorPtr)(CacheBlk &blk);
CacheBlkVisitorWrapper(BaseCache &_cache, VisitorPtr _visitor)
: cache(_cache), visitor(_visitor) {}
bool operator()(CacheBlk &blk) override {
return (cache.*visitor)(blk);
}
private:
BaseCache &cache;
VisitorPtr visitor;
};
/**
* Cache block visitor that determines if there are dirty blocks in a
* cache.
*
* Use with the forEachBlk method in the tag array to determine if the
* array contains dirty blocks.
*/
class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
{
public:
CacheBlkIsDirtyVisitor()
: _isDirty(false) {}
bool operator()(CacheBlk &blk) override {
if (blk.isDirty()) {
_isDirty = true;
return false;
} else {
return true;
}
}
/**
* Does the array contain a dirty line?
*
* @return true if yes, false otherwise.
*/
bool isDirty() const { return _isDirty; };
private:
bool _isDirty;
};
#endif //__MEM_CACHE_BASE_HH__

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src/mem/cache/cache.hh vendored
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@@ -46,221 +46,34 @@
/**
* @file
* Describes a cache based on template policies.
* Describes a cache
*/
#ifndef __MEM_CACHE_CACHE_HH__
#define __MEM_CACHE_CACHE_HH__
#include <cstdint>
#include <unordered_set>
#include "base/logging.hh" // fatal, panic, and warn
#include "enums/Clusivity.hh"
#include "base/types.hh"
#include "mem/cache/base.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
#include "mem/cache/tags/base.hh"
#include "params/Cache.hh"
#include "sim/eventq.hh"
#include "mem/packet.hh"
//Forward decleration
class BasePrefetcher;
class CacheBlk;
struct CacheParams;
class MSHR;
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
* storage @sa TagStore, \ref gem5MemorySystem "gem5 Memory System"
* A coherent cache that can be arranged in flexible topologies.
*/
class Cache : public BaseCache
{
protected:
/**
* The CPU-side port extends the base cache slave port with access
* functions for functional, atomic and timing requests.
*/
class CpuSidePort : public CacheSlavePort
{
private:
// a pointer to our specific cache implementation
Cache *cache;
protected:
virtual bool recvTimingSnoopResp(PacketPtr pkt);
virtual bool tryTiming(PacketPtr pkt);
virtual bool recvTimingReq(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(PacketPtr pkt);
virtual AddrRangeList getAddrRanges() const;
public:
CpuSidePort(const std::string &_name, Cache *_cache,
const std::string &_label);
};
/**
* Override the default behaviour of sendDeferredPacket to enable
* the memory-side cache port to also send requests based on the
* current MSHR status. This queue has a pointer to our specific
* cache implementation and is used by the MemSidePort.
*/
class CacheReqPacketQueue : public ReqPacketQueue
{
protected:
Cache &cache;
SnoopRespPacketQueue &snoopRespQueue;
public:
CacheReqPacketQueue(Cache &cache, MasterPort &port,
SnoopRespPacketQueue &snoop_resp_queue,
const std::string &label) :
ReqPacketQueue(cache, port, label), cache(cache),
snoopRespQueue(snoop_resp_queue) { }
/**
* Override the normal sendDeferredPacket and do not only
* consider the transmit list (used for responses), but also
* requests.
*/
virtual void sendDeferredPacket();
/**
* Check if there is a conflicting snoop response about to be
* send out, and if so simply stall any requests, and schedule
* a send event at the same time as the next snoop response is
* being sent out.
*/
bool checkConflictingSnoop(Addr addr)
{
if (snoopRespQueue.hasAddr(addr)) {
DPRINTF(CachePort, "Waiting for snoop response to be "
"sent\n");
Tick when = snoopRespQueue.deferredPacketReadyTime();
schedSendEvent(when);
return true;
}
return false;
}
};
/**
* The memory-side port extends the base cache master port with
* access functions for functional, atomic and timing snoops.
*/
class MemSidePort : public CacheMasterPort
{
private:
/** The cache-specific queue. */
CacheReqPacketQueue _reqQueue;
SnoopRespPacketQueue _snoopRespQueue;
// a pointer to our specific cache implementation
Cache *cache;
protected:
virtual void recvTimingSnoopReq(PacketPtr pkt);
virtual bool recvTimingResp(PacketPtr pkt);
virtual Tick recvAtomicSnoop(PacketPtr pkt);
virtual void recvFunctionalSnoop(PacketPtr pkt);
public:
MemSidePort(const std::string &_name, Cache *_cache,
const std::string &_label);
};
/** Tag and data Storage */
BaseTags *tags;
/** Prefetcher */
BasePrefetcher *prefetcher;
/** Temporary cache block for occasional transitory use */
CacheBlk *tempBlock;
/**
* This cache should allocate a block on a line-sized write miss.
*/
const bool doFastWrites;
/**
* Turn line-sized writes into WriteInvalidate transactions.
*/
void promoteWholeLineWrites(PacketPtr pkt);
/**
* Notify the prefetcher on every access, not just misses.
*/
const bool prefetchOnAccess;
/**
* Clusivity with respect to the upstream cache, determining if we
* fill into both this cache and the cache above on a miss. Note
* that we currently do not support strict clusivity policies.
*/
const Enums::Clusivity clusivity;
/**
* Determine if clean lines should be written back or not. In
* cases where a downstream cache is mostly inclusive we likely
* want it to act as a victim cache also for lines that have not
* been modified. Hence, we cannot simply drop the line (or send a
* clean evict), but rather need to send the actual data.
*/
const bool writebackClean;
/**
* Upstream caches need this packet until true is returned, so
* hold it for deletion until a subsequent call
*/
std::unique_ptr<Packet> pendingDelete;
/**
* Writebacks from the tempBlock, resulting on the response path
* in atomic mode, must happen after the call to recvAtomic has
* finished (for the right ordering of the packets). We therefore
* need to hold on to the packets, and have a method and an event
* to send them.
*/
PacketPtr tempBlockWriteback;
/**
* Send the outstanding tempBlock writeback. To be called after
* recvAtomic finishes in cases where the block we filled is in
* fact the tempBlock, and now needs to be written back.
*/
void writebackTempBlockAtomic() {
assert(tempBlockWriteback != nullptr);
PacketList writebacks{tempBlockWriteback};
doWritebacksAtomic(writebacks);
tempBlockWriteback = nullptr;
}
/**
* An event to writeback the tempBlock after recvAtomic
* finishes. To avoid other calls to recvAtomic getting in
* between, we create this event with a higher priority.
*/
EventFunctionWrapper writebackTempBlockAtomicEvent;
/**
* Store the outstanding requests that we are expecting snoop
* responses from so we can determine which snoop responses we
@@ -268,214 +81,45 @@ class Cache : public BaseCache
*/
std::unordered_set<RequestPtr> outstandingSnoop;
protected:
/**
* Does all the processing necessary to perform the provided request.
* @param pkt The memory request to perform.
* @param blk The cache block to be updated.
* @param lat The latency of the access.
* @param writebacks List for any writebacks that need to be performed.
* @return Boolean indicating whether the request was satisfied.
* Turn line-sized writes into WriteInvalidate transactions.
*/
bool access(PacketPtr pkt, CacheBlk *&blk,
Cycles &lat, PacketList &writebacks);
void promoteWholeLineWrites(PacketPtr pkt);
/**
*Handle doing the Compare and Swap function for SPARC.
*/
void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
PacketList &writebacks) override;
/**
* Find a block frame for new block at address addr targeting the
* given security space, assuming that the block is not currently
* in the cache. Append writebacks if any to provided packet
* list. Return free block frame. May return nullptr if there are
* no replaceable blocks at the moment.
*/
CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
Tick request_time) override;
/**
* Invalidate a cache block.
*
* @param blk Block to invalidate
*/
void invalidateBlock(CacheBlk *blk);
void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
Tick forward_time,
Tick request_time) override;
/**
* Maintain the clusivity of this cache by potentially
* invalidating a block. This method works in conjunction with
* satisfyRequest, but is separate to allow us to handle all MSHR
* targets before potentially dropping a block.
*
* @param from_cache Whether we have dealt with a packet from a cache
* @param blk The block that should potentially be dropped
*/
void maintainClusivity(bool from_cache, CacheBlk *blk);
void recvTimingReq(PacketPtr pkt) override;
/**
* Populates a cache block and handles all outstanding requests for the
* satisfied fill request. This version takes two memory requests. One
* contains the fill data, the other is an optional target to satisfy.
* @param pkt The memory request with the fill data.
* @param blk The cache block if it already exists.
* @param writebacks List for any writebacks that need to be performed.
* @param allocate Whether to allocate a block or use the temp block
* @return Pointer to the new cache block.
*/
CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
PacketList &writebacks, bool allocate);
void doWritebacks(PacketList& writebacks, Tick forward_time) override;
/**
* Determine whether we should allocate on a fill or not. If this
* cache is mostly inclusive with regards to the upstream cache(s)
* we always allocate (for any non-forwarded and cacheable
* requests). In the case of a mostly exclusive cache, we allocate
* on fill if the packet did not come from a cache, thus if we:
* are dealing with a whole-line write (the latter behaves much
* like a writeback), the original target packet came from a
* non-caching source, or if we are performing a prefetch or LLSC.
*
* @param cmd Command of the incoming requesting packet
* @return Whether we should allocate on the fill
*/
inline bool allocOnFill(MemCmd cmd) const override
{
return clusivity == Enums::mostly_incl ||
cmd == MemCmd::WriteLineReq ||
cmd == MemCmd::ReadReq ||
cmd == MemCmd::WriteReq ||
cmd.isPrefetch() ||
cmd.isLLSC();
}
void doWritebacksAtomic(PacketList& writebacks) override;
/*
* Handle a timing request that hit in the cache
*
* @param ptk The request packet
* @param blk The referenced block
* @param request_time The tick at which the block lookup is compete
*/
void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time);
/*
* Handle a timing request that missed in the cache
*
* @param ptk The request packet
* @param blk The referenced block
* @param forward_time The tick at which we can process dependent requests
* @param request_time The tick at which the block lookup is compete
*/
void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time,
Tick request_time);
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
*/
void recvTimingReq(PacketPtr pkt);
/**
* Insert writebacks into the write buffer
*/
void doWritebacks(PacketList& writebacks, Tick forward_time);
/**
* Send writebacks down the memory hierarchy in atomic mode
*/
void doWritebacksAtomic(PacketList& writebacks);
/**
* Handling the special case of uncacheable write responses to
* make recvTimingResp less cluttered.
*/
void handleUncacheableWriteResp(PacketPtr pkt);
/**
* Service non-deferred MSHR targets using the received response
*
* Iterates through the list of targets that can be serviced with
* the current response. Any writebacks that need to performed
* must be appended to the writebacks parameter.
*
* @param mshr The MSHR that corresponds to the reponse
* @param pkt The response packet
* @param blk The reference block
* @param writebacks List of writebacks that need to be performed
*/
void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
PacketList& writebacks);
PacketList& writebacks) override;
/**
* Handles a response (cache line fill/write ack) from the bus.
* @param pkt The response packet
*/
void recvTimingResp(PacketPtr pkt);
void recvTimingSnoopReq(PacketPtr pkt) override;
/**
* Snoops bus transactions to maintain coherence.
* @param pkt The current bus transaction.
*/
void recvTimingSnoopReq(PacketPtr pkt);
void recvTimingSnoopResp(PacketPtr pkt) override;
/**
* Handle a snoop response.
* @param pkt Snoop response packet
*/
void recvTimingSnoopResp(PacketPtr pkt);
/**
* Handle a request in atomic mode that missed in this cache
*
* Creates a downstream request, sends it to the memory below and
* handles the response. As we are in atomic mode all operations
* are performed immediately.
*
* @param pkt The packet with the requests
* @param blk The referenced block
* @parma writebacks A list with packets for any performed writebacks
* @return Cycles for handling the request
*/
Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
PacketList &writebacks);
PacketList &writebacks) override;
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
* @return The number of ticks required for the access.
*/
Tick recvAtomic(PacketPtr pkt);
Tick recvAtomic(PacketPtr pkt) override;
/**
* Snoop for the provided request in the cache and return the estimated
* time taken.
* @param pkt The memory request to snoop
* @return The number of ticks required for the snoop.
*/
Tick recvAtomicSnoop(PacketPtr pkt);
Tick recvAtomicSnoop(PacketPtr pkt) override;
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
* @param fromCpuSide from the CPU side port or the memory side port
*/
void functionalAccess(PacketPtr pkt, bool fromCpuSide);
/**
* Perform any necessary updates to the block and perform any data
* exchange between the packet and the block. The flags of the
* packet are also set accordingly.
*
* @param pkt Request packet from upstream that hit a block
* @param blk Cache block that the packet hit
* @param deferred_response Whether this hit is to block that
* originally missed
* @param pending_downgrade Whether the writable flag is to be removed
*
* @return True if the block is to be invalidated
*/
void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
bool deferred_response = false,
bool pending_downgrade = false);
bool pending_downgrade = false) override;
void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
bool already_copied, bool pending_inval);
@@ -495,131 +139,31 @@ class Cache : public BaseCache
uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
bool is_timing, bool is_deferred, bool pending_inval);
/**
* Evict a cache block.
*
* Performs a writeback if necesssary and invalidates the block
*
* @param blk Block to invalidate
* @return A packet with the writeback, can be nullptr
*/
M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk);
M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
/**
* Evict a cache block.
*
* Performs a writeback if necesssary and invalidates the block
*
* @param blk Block to invalidate
* @param writebacks Return a list of packets with writebacks
*/
virtual void evictBlock(CacheBlk *blk, PacketList &writebacks);
/**
* Create a writeback request for the given block.
* @param blk The block to writeback.
* @return The writeback request for the block.
*/
PacketPtr writebackBlk(CacheBlk *blk);
/**
* Create a writeclean request for the given block.
* @param blk The block to write clean
* @param dest The destination of this clean operation
* @return The write clean packet for the block.
*/
PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);
void evictBlock(CacheBlk *blk, PacketList &writebacks) override;
/**
* Create a CleanEvict request for the given block.
*
* @param blk The block to evict.
* @return The CleanEvict request for the block.
*/
PacketPtr cleanEvictBlk(CacheBlk *blk);
void memWriteback() override;
void memInvalidate() override;
bool isDirty() const override;
/**
* Cache block visitor that writes back dirty cache blocks using
* functional writes.
*
* \return Always returns true.
*/
bool writebackVisitor(CacheBlk &blk);
/**
* Cache block visitor that invalidates all blocks in the cache.
*
* @warn Dirty cache lines will not be written back to memory.
*
* \return Always returns true.
*/
bool invalidateVisitor(CacheBlk &blk);
/**
* Create an appropriate downstream bus request packet for the
* given parameters.
* @param cpu_pkt The miss that needs to be satisfied.
* @param blk The block currently in the cache corresponding to
* cpu_pkt (nullptr if none).
* @param needsWritable Indicates that the block must be writable
* even if the request in cpu_pkt doesn't indicate that.
* @return A new Packet containing the request, or nullptr if the
* current request in cpu_pkt should just be forwarded on.
*/
PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
bool needsWritable) const;
/**
* Return the next queue entry to service, either a pending miss
* from the MSHR queue, a buffered write from the write buffer, or
* something from the prefetcher. This function is responsible
* for prioritizing among those sources on the fly.
*/
QueueEntry* getNextQueueEntry();
bool needsWritable) const override;
/**
* Send up a snoop request and find cached copies. If cached copies are
* found, set the BLOCK_CACHED flag in pkt.
*/
bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const;
/**
* Return whether there are any outstanding misses.
*/
bool outstandingMisses() const
{
return !mshrQueue.isEmpty();
}
CacheBlk *findBlock(Addr addr, bool is_secure) const {
return tags->findBlock(addr, is_secure);
}
bool inCache(Addr addr, bool is_secure) const override {
return (tags->findBlock(addr, is_secure) != 0);
}
bool inMissQueue(Addr addr, bool is_secure) const override {
return (mshrQueue.findMatch(addr, is_secure) != 0);
}
/**
* Find next request ready time from among possible sources.
*/
Tick nextQueueReadyTime() const;
bool isCachedAbove(PacketPtr pkt, bool is_timing = true);
public:
/** Instantiates a basic cache object. */
Cache(const CacheParams *p);
/** Non-default destructor is needed to deallocate memory. */
virtual ~Cache();
void regStats() override;
/**
* Take an MSHR, turn it into a suitable downstream packet, and
* send it out. This construct allows a queue entry to choose a suitable
@@ -628,81 +172,7 @@ class Cache : public BaseCache
* @param mshr The MSHR to turn into a packet and send
* @return True if the port is waiting for a retry
*/
bool sendMSHRQueuePacket(MSHR* mshr);
/**
* Similar to sendMSHR, but for a write-queue entry
* instead. Create the packet, and send it, and if successful also
* mark the entry in service.
*
* @param wq_entry The write-queue entry to turn into a packet and send
* @return True if the port is waiting for a retry
*/
bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
/** serialize the state of the caches
* We currently don't support checkpointing cache state, so this panics.
*/
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
/**
* Wrap a method and present it as a cache block visitor.
*
* For example the forEachBlk method in the tag arrays expects a
* callable object/function as their parameter. This class wraps a
* method in an object and presents callable object that adheres to
* the cache block visitor protocol.
*/
class CacheBlkVisitorWrapper : public CacheBlkVisitor
{
public:
typedef bool (Cache::*VisitorPtr)(CacheBlk &blk);
CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor)
: cache(_cache), visitor(_visitor) {}
bool operator()(CacheBlk &blk) override {
return (cache.*visitor)(blk);
}
private:
Cache &cache;
VisitorPtr visitor;
};
/**
* Cache block visitor that determines if there are dirty blocks in a
* cache.
*
* Use with the forEachBlk method in the tag array to determine if the
* array contains dirty blocks.
*/
class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
{
public:
CacheBlkIsDirtyVisitor()
: _isDirty(false) {}
bool operator()(CacheBlk &blk) override {
if (blk.isDirty()) {
_isDirty = true;
return false;
} else {
return true;
}
}
/**
* Does the array contain a dirty line?
*
* \return true if yes, false otherwise.
*/
bool isDirty() const { return _isDirty; };
private:
bool _isDirty;
bool sendMSHRQueuePacket(MSHR* mshr) override;
};
#endif // __MEM_CACHE_CACHE_HH__

2
src/mem/cache/mshr.cc vendored
View File

@@ -587,7 +587,7 @@ MSHR::checkFunctional(PacketPtr pkt)
}
bool
MSHR::sendPacket(Cache &cache)
MSHR::sendPacket(BaseCache &cache)
{
return cache.sendMSHRQueuePacket(this);
}

4
src/mem/cache/mshr.hh vendored
View File

@@ -53,7 +53,7 @@
#include "base/printable.hh"
#include "mem/cache/queue_entry.hh"
class Cache;
class BaseCache;
/**
* Miss Status and handling Register. This class keeps all the information
@@ -263,7 +263,7 @@ class MSHR : public QueueEntry, public Printable
assert(inService); return postDowngrade;
}
bool sendPacket(Cache &cache);
bool sendPacket(BaseCache &cache);
bool allocOnFill() const {
return targets.allocOnFill;

4
src/mem/cache/queue_entry.hh vendored
View File

@@ -51,7 +51,7 @@
#include "mem/packet.hh"
class Cache;
class BaseCache;
/**
* A queue entry base class, to be used by both the MSHRs and
@@ -102,7 +102,7 @@ class QueueEntry : public Packet::SenderState
* Send this queue entry as a downstream packet, with the exact
* behaviour depending on the specific entry type.
*/
virtual bool sendPacket(Cache &cache) = 0;
virtual bool sendPacket(BaseCache &cache) = 0;
};

2
src/mem/cache/write_queue_entry.cc vendored
View File

@@ -139,7 +139,7 @@ WriteQueueEntry::checkFunctional(PacketPtr pkt)
}
bool
WriteQueueEntry::sendPacket(Cache &cache)
WriteQueueEntry::sendPacket(BaseCache &cache)
{
return cache.sendWriteQueuePacket(this);
}

4
src/mem/cache/write_queue_entry.hh vendored
View File

@@ -54,7 +54,7 @@
#include "base/printable.hh"
#include "mem/cache/queue_entry.hh"
class Cache;
class BaseCache;
/**
* Write queue entry
@@ -101,7 +101,7 @@ class WriteQueueEntry : public QueueEntry, public Printable
/** WriteQueueEntry list iterator. */
typedef List::iterator Iterator;
bool sendPacket(Cache &cache);
bool sendPacket(BaseCache &cache);
private: