Now that delta events are handled explicitly by the scheduler, there's
no reason to run the readyEvent inline when returning from a pause. The
delta events will necessarily be run after the evaluate and update
phases.
Change-Id: Iad6d431a87742354e3a46a0fb44c309aa785ea60
Reviewed-on: https://gem5-review.googlesource.com/12214
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Rather than delegating them entirely to the gem5 event queue and using
priorities to ensure the right thing happens, this change adds a few
new structures which keep track of them and give the scheduler more
control over what happens and in what order. The old scheme was mostly
correct, but there were some competing situations which made it next
to impossible to make everything happen at the right time.
Change-Id: I43f4dd6ddfa488a31073c0318bb41369b1a6117d
Reviewed-on: https://gem5-review.googlesource.com/12213
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
In the previous implementation, messages are randomly inserted with
delays only if both RubySystem and MessageBuffer randomization flags
are set true. However, to find race conditions and cover more slicc
transitions, ruby random testers rely on setting RubySystem flag to
turn on randomization on all message buffers.
As a fix, this patch enables a message buffer to have randomization
when either RubySystem or its own flag is set.
Change-Id: I1e076908ff07e5846ebad4f4fc1c8f28d40bbfd4
Reviewed-on: https://gem5-review.googlesource.com/12784
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Those messages are very implementation specific and don't (generally)
affect correctness. This makes it easier to ignore info messages based
on their number.
This change also makes the output checker ignore a similarly styled
message gem5 generates. We should consider making gem5 not generate
that message and have it generate another message instead which is
specific to gem5. We would need to filter that out too when comparing
results.
Change-Id: I93b9e2d547b6259512db091cfc557d21f86f4a3d
Reviewed-on: https://gem5-review.googlesource.com/12086
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This change adds code which keeps track of ports and interfaces which
are being bound to be finalized later, and the actual port binding of
interfaces and recursive binding port ports.
Change-Id: Ifa885ed44b667254762cc101580be4f0a7d7a131
Reviewed-on: https://gem5-review.googlesource.com/12084
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
It seems that implementing more of systemc makes the compiler think it
wants an implementation, and so the build fails with linker errors.
Change-Id: I6f0b031f300b0ad60dac8b4462b8f4d466aa7dfa
Reviewed-on: https://gem5-review.googlesource.com/12081
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Normally delta notifications would be created during the evaluation or
update phases, and so there isn't any problem with them cutting in
front of those stages. When the simulation is paused however, those
notifications could be waiting before the ready event starts and could
preempt it.
This change adds a check for that situation to the end of the pause
event and runs the evalution and update stages inline if necessary.
Change-Id: I4477b2ae8e7980406df00ba7320ae2a24ae2da9b
Reviewed-on: https://gem5-review.googlesource.com/12080
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This change ignores the rule that sc_exports all have to be bound
exactly once and only by the end of elaboration. If it's bound more
than once, then the earlier binding will be overwritten, and if it's
not bound at all then it will act like a null pointer. To accomodate
doing those checks in the future, the sc_export_base constructor and
destructor are in the .cc file even though they do very little so that
they can be extended to track a list of all exports which exist.
Change-Id: Ie9a3416b8fa87bca55bc9f87f3238c4de3c2e729
Reviewed-on: https://gem5-review.googlesource.com/12079
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
That happens when an update is requested before the initialization
phase has started. In that case, the update phase will be manually run
and no event needs to be scheduled, even if that was possible.
Change-Id: I2008e29064d282f82bd1935dbe5b94407aa925b0
Reviewed-on: https://gem5-review.googlesource.com/12078
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This is less efficient when modules are destroyed since the list isn't
sorted, and each module needs to find its own entry to remove. The
benefit is that entries added to the end of the list while the list is
being iterated over will still be included, and that the order the
modules are added will be preserved so that it matches what the order
in the regression tests.
Change-Id: I5af5d15f316fa58561e8fd9ca77f667ddc8b2c5e
Reviewed-on: https://gem5-review.googlesource.com/12077
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
The kernel can set the event queue during its own construction which
will ensure that the scheduler can schedule events as early as
possible.
Change-Id: I0e47ca0a667e77d36c97860cd7c6b7577415c801
Reviewed-on: https://gem5-review.googlesource.com/12073
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This is necessary if an sc_time object is constructed globally, either
directly or indirectly, before python is available to fix the
timescale. The call will be deferred until the interpretter is up and
ready.
Change-Id: I486c0a90d44a0e0f0ad8c530b7148e1cff04a5cc
Reviewed-on: https://gem5-review.googlesource.com/12070
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This change pulls the systemc python module creation code out of
sc_main and puts it into a more general purpose python.hh and
python.cc which can be used by other code to add other entries into
that module without having to track that in a central place.
This change also adds a mechanism for notifying C++ code that the
embedded python interpretter is up and ready to interact with in case
it needs to call some python only functionality. An example of that is
the code which tracks and then fixes the timescale for the simulator.
Change-Id: I9afcd5a089b21d23ebc1b5fdb6f643ae2f7e5f11
Reviewed-on: https://gem5-review.googlesource.com/12069
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
The Accellera implementation statically allocates the buffer it uses to
build the unique names and only allocates the name generator if it's
going to be used for a particular module. I assume that's to avoid
allocating a large buffer if it's not going to be used.
In this implementation, I use an std::string which manages its own
memory and so shouldn't need to be selectively allocated. I also use a
string stream to construct the name instead of sprintf.
Change-Id: If92c68586a85b5d27c067a75a6e9ebbf00d8c785
Reviewed-on: https://gem5-review.googlesource.com/12066
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Strips off superfluous inline specifiers in header file.
Changes return types and parameters that deal with strings
to include the const& specifiers.
Change-Id: I570b1801abb059b91216f0223458d00963b9ca1c
Reviewed-on: https://gem5-review.googlesource.com/12111
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Some members were defined as public when they should have been
privately declared so these were moved to the appropriate spot.
The operator[] had inline specified for for an in-class
definition which is redundant since inline definitions are
always implicitly inline.
Private members had the leading underscore applied to them to
denote that they're private (consistent with style guide).
Changed static const defined class variable into a constexpr
with brace-list initialization.
Change-Id: If3054416b57827d1542e9ebab428d67d0e767723
Reviewed-on: https://gem5-review.googlesource.com/12110
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The AuxVector class is responsible for holding Process data.
The data that it holds is normally setup by an OS kernel in
the process address space. The purpose behind doing this is
to pass in information that the process will need for various
reasons. (Check out the enum in the header file for an idea of
what the AuxVector holds.)
The AuxVector struct was changed into a class and encapsulation
methods were added to protect access to the member variables.
The host ISA may have a different endianness than the simulated
ISA. Since data is passed between the process address space and
the simulator for auxiliary vectors, we need to worry about
maintaining endianness for the right context.
Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9
Reviewed-on: https://gem5-review.googlesource.com/12109
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
GNU as 2.31.1 checks if the input and output files are the same:
Assembler messages:
Fatal error: The input and output files must be distinct
The check already does not work for llvm-as which has a different
output format.
Since it is too hard to maintain the check correctly for all possible
assemblers, it is better to just remove it completely.
Change-Id: I38a993ab83ca83d4a2f5e77820d2ca903f70c6ac
Reviewed-on: https://gem5-review.googlesource.com/12403
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
The hash() function must be bijective for the skewed caches to work,
however when the hashing is done on top of a one-bit address, the
MSB and LSB refer to the same bit, and therefore their xor will
always be zero.
This patch adds a fatal error to not allow the user to set an invalid
value for the number of sets that would generate that bug.
As a side note, the missing header for the bitfields functions has
been added.
Change-Id: I35a03ac5fdc4debb091f7f2db5db33568d0b0021
Reviewed-on: https://gem5-review.googlesource.com/12724
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
From GCC 8.1 on GCC issues a warning when using memset et al on structs and
classes. With the way gem5 builds, this actually prevents successful
builds.
Instead of using a pointer with SCSIReply as type, we cast to a void
pointer to avoid the message. On the way we wrap the memset call into a
method of SCSIReply called reset for better code readability.
Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: I3ed3fd9714be5d253aba01ca00b1863e1ae5cb68
Reviewed-on: https://gem5-review.googlesource.com/12685
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
UART_RSR shows errors with the transmission and UART_ECR can clear
those (according to PL011 Technical Reference Manual Revision r1p4). As
these transmission errors never occur, they are implemented as RAZ/WI.
Both registers exist at the same offset 0x004. RSR is read-only, ECR is
write-only.
Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02
Reviewed-on: https://gem5-review.googlesource.com/12686
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Providing a configurable fair scheduling policy based on utilization;
utilization is directly proportional to a score which is inversely
proportional to the QoS priority. It is meant to avoid starvation of low
priority packets.
Users can tune the policy by adjusting the weight parameter (weight of
the following formula)
new_score = ((1.0 - weight) * old_score) + (weight * served_bytes)
Change-Id: I7679e234b916c57ebed06cec0ff3cff3cf2aef22
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12359
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Currently 'Clock period in ticks' stat is not accessible in power equations .
This patch adds a variable 'clock_period' to be referenced to get the Clock period in
ticks
Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com>
Change-Id: Icac6a2e2003ed75d1680180e53343b0203139d72
Reviewed-on: https://gem5-review.googlesource.com/12664
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Sometimes it's easier to debug gem5 built with ASan enabled. This CL fixes
some build error when using --with-asan.
Bug: None
Test: ./scripts/build_gem5 --with-asan --with-ubsan build/ARM/gem5.debug
Change-Id: Iaaaaebc3f25749e11f97bf454ddd0153b3de56e7
Reviewed-on: https://gem5-review.googlesource.com/12511
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
When doing EL0/1 translation in stage2, the
physical address size will be defined by the
hypervisor (via VTCR_EL2.ps, not TCR.ips).
See D10.2.121 of the ARM ARM.
Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12552
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
"4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug
where if an atomic request that fills in using the tempBlock it will
not evict it when it finishes handling the request as it should. This
triggers an assertion. This change fixes this bug.
Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12644
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
