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Pl011: Added registers UART_RSR/UART_ECR

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UART_RSR shows errors with the transmission and UART_ECR can clear
those (according to PL011 Technical Reference Manual Revision r1p4).  As
these transmission errors never occur, they are implemented as RAZ/WI.

Both registers exist at the same offset 0x004. RSR is read-only, ECR is
write-only.

Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02
Reviewed-on: https://gem5-review.googlesource.com/12686
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Maurice Becker
2018-09-18 10:27:40 +02:00
committed by MadMaurice
parent 1fdf576ec7
commit 95143897fc
2 changed files with 7 additions and 0 deletions
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5
src/dev/arm/pl011.cc
View File

@@ -92,6 +92,9 @@ Pl011::read(PacketPtr pkt)
}
}
break;
case UART_RSR:
data = 0x0; // We never have errors
break;
case UART_FR:
data =
UART_FR_CTS | // Clear To Send
@@ -205,6 +208,8 @@ Pl011::write(PacketPtr pkt)
clearInterrupts(UART_TXINTR);
raiseInterrupts(UART_TXINTR);
break;
case UART_ECR: // clears errors, ignore
break;
case UART_CR:
control = data;
break;

2
src/dev/arm/pl011.hh
View File

@@ -118,6 +118,8 @@ class Pl011 : public Uart, public AmbaDevice
protected: // Registers
static const uint64_t AMBA_ID = ULL(0xb105f00d00341011);
static const int UART_DR = 0x000;
static const int UART_RSR = 0x004;
static const int UART_ECR = 0x004;
static const int UART_FR = 0x018;
static const int UART_FR_CTS = 0x001;
static const int UART_FR_RXFE = 0x010;