Giacomo Travaglini
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e7a1636889
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dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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2019-04-02 16:20:54 +00:00 |
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Jairo Balart
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66c80fcb44
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dev-arm: cleanup of gicv3 CPU interface code and fixes
Change-Id: I4643140f60da4dc9179b5bfed1e3ddd7c2f23091
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16484
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-03-14 10:54:16 +00:00 |
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Gabe Black
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2b80f588ab
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arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.
Other dev code was already switched over. This code was written before
the switch over (or unaware of it), and checked in after.
Change-Id: Ibb9e9e4300d01cc46e4dae668274debc2a4989ba
Reviewed-on: https://gem5-review.googlesource.com/c/15755
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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2019-01-22 19:42:15 +00:00 |
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Jairo Balart
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93c7fa5731
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dev-arm: Add a GICv3 model
Change-Id: Ib0067fc743f84ff7be9f12d2fc33ddf63736bdd1
Reviewed-on: https://gem5-review.googlesource.com/c/13436
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-01-10 16:29:30 +00:00 |
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