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arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model.

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Other dev code was already switched over. This code was written before
the switch over (or unaware of it), and checked in after.

Change-Id: Ibb9e9e4300d01cc46e4dae668274debc2a4989ba
Reviewed-on: https://gem5-review.googlesource.com/c/15755
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Gabe Black
2019-01-21 13:14:55 -08:00
parent 0f024be0ca
commit 2b80f588ab
2 changed files with 54 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

114
src/dev/arm/gic_v3_cpu_interface.cc
View File

@@ -96,10 +96,10 @@ Gicv3CPUInterface::getHCREL2IMO()
}
}
ArmISA::MiscReg
RegVal
Gicv3CPUInterface::readMiscReg(int misc_reg)
{
ArmISA::MiscReg value = isa->readMiscRegNoEffect(misc_reg);
RegVal value = isa->readMiscRegNoEffect(misc_reg);
bool hcr_fmo = getHCREL2FMO();
bool hcr_imo = getHCREL2IMO();
@@ -235,7 +235,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
int lr_idx = getHPPVILR();
if (lr_idx >= 0) {
ArmISA::MiscReg lr =
RegVal lr =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
Gicv3::GroupId group =
lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
@@ -263,7 +263,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
int lr_idx = getHPPVILR();
if (lr_idx >= 0) {
ArmISA::MiscReg lr =
RegVal lr =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
Gicv3::GroupId group =
lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
@@ -340,7 +340,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
case MISCREG_ICV_BPR1_EL1: {
Gicv3::GroupId group =
misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
ArmISA::MiscReg ich_vmcr_el2 =
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
bool sat_inc = false;
@@ -420,7 +420,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
uint32_t int_id = Gicv3::INTID_SPURIOUS;
if (lr_idx >= 0) {
ArmISA::MiscReg lr =
RegVal lr =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
if (!(lr & ICH_LR_EL2_GROUP) && hppviCanPreempt(lr_idx)) {
@@ -473,7 +473,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
uint32_t int_id = Gicv3::INTID_SPURIOUS;
if (lr_idx >= 0) {
ArmISA::MiscReg lr =
RegVal lr =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
if (lr & ICH_LR_EL2_GROUP && hppviCanPreempt(lr_idx)) {
@@ -506,21 +506,21 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
if (haveEL(EL3) && !distributor->DS) {
// DIB is RO alias of ICC_SRE_EL3.DIB
// DFB is RO alias of ICC_SRE_EL3.DFB
ArmISA::MiscReg icc_sre_el3 =
RegVal icc_sre_el3 =
isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
dfb = icc_sre_el3 & ICC_SRE_EL3_DFB;
dib = icc_sre_el3 & ICC_SRE_EL3_DIB;
} else if (haveEL(EL3) && distributor->DS) {
// DIB is RW alias of ICC_SRE_EL3.DIB
// DFB is RW alias of ICC_SRE_EL3.DFB
ArmISA::MiscReg icc_sre_el3 =
RegVal icc_sre_el3 =
isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
dfb = icc_sre_el3 & ICC_SRE_EL3_DFB;
dib = icc_sre_el3 & ICC_SRE_EL3_DIB;
} else if ((!haveEL(EL3) || distributor->DS) and haveEL(EL2)) {
// DIB is RO alias of ICC_SRE_EL2.DIB
// DFB is RO alias of ICC_SRE_EL2.DFB
ArmISA::MiscReg icc_sre_el2 =
RegVal icc_sre_el2 =
isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL2);
dfb = icc_sre_el2 & ICC_SRE_EL2_DFB;
dib = icc_sre_el2 & ICC_SRE_EL2_DIB;
@@ -588,7 +588,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
case MISCREG_ICV_CTLR_EL1: {
value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
(7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
ArmISA::MiscReg ich_vmcr_el2 =
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
if (ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) {
@@ -612,9 +612,9 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
value |= ICC_CTLR_EL3_RSS | ICC_CTLR_EL3_A3V | (0 << 11) |
((PRIORITY_BITS - 1) << 8);
// Aliased bits...
ArmISA::MiscReg icc_ctlr_el1_ns =
RegVal icc_ctlr_el1_ns =
isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
ArmISA::MiscReg icc_ctlr_el1_s =
RegVal icc_ctlr_el1_s =
isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
if (icc_ctlr_el1_ns & ICC_CTLR_EL1_EOIMODE) {
@@ -653,9 +653,9 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
value = 0;
// Scan list registers and fill in the U, NP and EOI bits
eoiMaintenanceInterruptStatus((uint32_t *) &value);
ArmISA::MiscReg ich_hcr_el2 =
RegVal ich_hcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
ArmISA::MiscReg ich_vmcr_el2 =
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
if (ich_hcr_el2 &
@@ -723,7 +723,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
value = 0;
for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
ArmISA::MiscReg lr =
RegVal lr =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
if ((lr & ICH_LR_EL2_STATE_MASK) == 0 &&
@@ -764,7 +764,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
}
void
Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
{
bool do_virtual_update = false;
DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): "
@@ -864,7 +864,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
// No LR found matching
virtualIncrementEOICount();
} else {
ArmISA::MiscReg lr =
RegVal lr =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
Gicv3::GroupId lr_group =
lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
@@ -941,7 +941,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
// No LR found matching
virtualIncrementEOICount();
} else {
ArmISA::MiscReg lr =
RegVal lr =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
Gicv3::GroupId lr_group =
lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
@@ -1115,7 +1115,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
case MISCREG_ICV_BPR1_EL1: {
Gicv3::GroupId group =
misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
ArmISA::MiscReg ich_vmcr_el2 =
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
@@ -1176,7 +1176,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
mask = ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE;
}
ArmISA::MiscReg old_val =
RegVal old_val =
isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
old_val &= ~mask;
val = old_val | (val & mask);
@@ -1184,7 +1184,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
}
case MISCREG_ICV_CTLR_EL1: {
ArmISA::MiscReg ich_vmcr_el2 =
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
ich_vmcr_el2 = insertBits(ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT,
val & ICC_CTLR_EL1_CBPR ? 1 : 0);
@@ -1197,9 +1197,9 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
case MISCREG_ICC_MCTLR:
case MISCREG_ICC_CTLR_EL3: {
ArmISA::MiscReg icc_ctlr_el1_s =
RegVal icc_ctlr_el1_s =
isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
ArmISA::MiscReg icc_ctlr_el1_ns =
RegVal icc_ctlr_el1_ns =
isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
// ICC_CTLR_EL1(NS).EOImode is an alias of
@@ -1234,7 +1234,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S, icc_ctlr_el1_s);
isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS, icc_ctlr_el1_ns);
// Only ICC_CTLR_EL3_EOIMODE_EL3 is writable
ArmISA::MiscReg old_icc_ctlr_el3 =
RegVal old_icc_ctlr_el3 =
isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
old_icc_ctlr_el3 &= ~(ICC_CTLR_EL3_EOIMODE_EL3 | ICC_CTLR_EL3_RM);
val = old_icc_ctlr_el3 |
@@ -1257,7 +1257,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
* NS access and Group 0 is inaccessible to NS: return the
* NS view of the current priority
*/
ArmISA::MiscReg old_icc_pmr_el1 =
RegVal old_icc_pmr_el1 =
isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
if (!(old_icc_pmr_el1 & 0x80)) {
@@ -1284,7 +1284,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
case MISCREG_ICV_IGRPEN0_EL1: {
bool enable = val & 0x1;
ArmISA::MiscReg ich_vmcr_el2 =
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
ich_vmcr_el2 = insertBits(ich_vmcr_el2,
ICH_VMCR_EL2_VENG0_SHIFT, enable);
@@ -1304,7 +1304,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
case MISCREG_ICV_IGRPEN1_EL1: {
bool enable = val & 0x1;
ArmISA::MiscReg ich_vmcr_el2 =
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
ich_vmcr_el2 = insertBits(ich_vmcr_el2,
ICH_VMCR_EL2_VENG1_SHIFT, enable);
@@ -1407,7 +1407,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
} else if (haveEL(EL3) && distributor->DS) {
// DIB is RW alias of ICC_SRE_EL3.DIB
// DFB is RW alias of ICC_SRE_EL3.DFB
ArmISA::MiscReg icc_sre_el3 =
RegVal icc_sre_el3 =
isa->readMiscRegNoEffect(MISCREG_ICC_SRE_EL3);
icc_sre_el3 = insertBits(icc_sre_el3, ICC_SRE_EL3_DFB, dfb);
icc_sre_el3 = insertBits(icc_sre_el3, ICC_SRE_EL3_DIB, dib);
@@ -1451,7 +1451,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
// Enforce RES0 bits in priority field, 5 of 8 bits used
val = insertBits(val, ICH_LRC_PRIORITY_SHIFT + 2,
ICH_LRC_PRIORITY_SHIFT, 0);
ArmISA::MiscReg old_val = isa->readMiscRegNoEffect(misc_reg);
RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
val = (old_val & 0xffffffff) | (val << 32);
do_virtual_update = true;
break;
@@ -1459,7 +1459,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, ArmISA::MiscReg val)
case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
// AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
ArmISA::MiscReg old_val = isa->readMiscRegNoEffect(misc_reg);
RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
val = (old_val & 0xffffffff00000000) | (val & 0xffffffff);
do_virtual_update = true;
break;
@@ -1517,7 +1517,7 @@ int
Gicv3CPUInterface::virtualFindActive(uint32_t int_id)
{
for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
ArmISA::MiscReg lr =
RegVal lr =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
uint32_t lr_intid = bits(lr, 31, 0);
@@ -1597,7 +1597,7 @@ void
Gicv3CPUInterface::dropPriority(Gicv3::GroupId group)
{
int apr_misc_reg;
ArmISA::MiscReg apr;
RegVal apr;
apr_misc_reg = group == Gicv3::G0S ?
MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
apr = isa->readMiscRegNoEffect(apr_misc_reg);
@@ -1625,10 +1625,8 @@ Gicv3CPUInterface::virtualDropPriority()
int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
for (int i = 0; i < apr_max; i++) {
ArmISA::MiscReg vapr0 =
isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
ArmISA::MiscReg vapr1 =
isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
RegVal vapr1 = isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
if (!vapr0 && !vapr1) {
continue;
@@ -1662,7 +1660,7 @@ Gicv3CPUInterface::activateIRQ(uint32_t int_id, Gicv3::GroupId group)
int reg_bit = apr_bit % 32;
int apr_idx = group == Gicv3::G0S ?
MISCREG_ICC_AP0R0_EL1 : MISCREG_ICC_AP1R0_EL1;
ArmISA::MiscReg apr = isa->readMiscRegNoEffect(apr_idx);
RegVal apr = isa->readMiscRegNoEffect(apr_idx);
apr |= (1 << reg_bit);
isa->setMiscRegNoEffect(apr_idx, apr);
@@ -1682,7 +1680,7 @@ void
Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
{
// Update active priority registers.
ArmISA::MiscReg lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
lr_idx);
Gicv3::GroupId group = lr & ICH_LR_EL2_GROUP ? Gicv3::G1NS : Gicv3::G0S;
uint8_t prio = bits(lr, 55, 48) & 0xf8;
@@ -1691,7 +1689,7 @@ Gicv3CPUInterface::virtualActivateIRQ(uint32_t lr_idx)
int reg_bit = apr_bit % 32;
int apr_idx = group == Gicv3::G0S ?
MISCREG_ICH_AP0R0_EL2 + reg_no : MISCREG_ICH_AP1R0_EL2 + reg_no;
ArmISA::MiscReg apr = isa->readMiscRegNoEffect(apr_idx);
RegVal apr = isa->readMiscRegNoEffect(apr_idx);
apr |= (1 << reg_bit);
isa->setMiscRegNoEffect(apr_idx, apr);
// Move interrupt state from pending to active.
@@ -1719,7 +1717,7 @@ Gicv3CPUInterface::deactivateIRQ(uint32_t int_id, Gicv3::GroupId group)
void
Gicv3CPUInterface::virtualDeactivateIRQ(int lr_idx)
{
ArmISA::MiscReg lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
lr_idx);
if (lr & ICH_LR_EL2_HW) {
@@ -1790,7 +1788,7 @@ Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
uint32_t
Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group)
{
ArmISA::MiscReg ich_vmcr_el2 =
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
@@ -1828,8 +1826,7 @@ Gicv3CPUInterface::isEOISplitMode()
bool
Gicv3CPUInterface::virtualIsEOISplitMode()
{
ArmISA::MiscReg ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
return ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM;
}
@@ -1897,7 +1894,7 @@ Gicv3CPUInterface::virtualUpdate()
int lr_idx = getHPPVILR();
if (lr_idx >= 0) {
ArmISA::MiscReg ich_lr_el2 =
RegVal ich_lr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
if (hppviCanPreempt(lr_idx)) {
@@ -1909,8 +1906,7 @@ Gicv3CPUInterface::virtualUpdate()
}
}
ArmISA::MiscReg ich_hcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
if (ich_hcr_el2 & ICH_HCR_EL2_EN) {
if (maintenanceInterruptStatus()) {
@@ -1940,8 +1936,7 @@ int
Gicv3CPUInterface::getHPPVILR()
{
int idx = -1;
ArmISA::MiscReg ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
if (!(ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) {
// VG0 and VG1 disabled...
@@ -1951,7 +1946,7 @@ Gicv3CPUInterface::getHPPVILR()
uint8_t highest_prio = 0xff;
for (int i = 0; i < 16; i++) {
ArmISA::MiscReg ich_lri_el2 =
RegVal ich_lri_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + i);
uint8_t state = bits(ich_lri_el2, 63, 62);
@@ -1985,8 +1980,7 @@ Gicv3CPUInterface::getHPPVILR()
bool
Gicv3CPUInterface::hppviCanPreempt(int lr_idx)
{
ArmISA::MiscReg lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 +
lr_idx);
RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
if (!(isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2) & ICH_HCR_EL2_EN)) {
// virtual interface is disabled
@@ -2024,7 +2018,7 @@ Gicv3CPUInterface::virtualHighestActivePriority()
uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
for (int i = 0; i < num_aprs; i++) {
ArmISA::MiscReg vapr =
RegVal vapr =
isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i) |
isa->readMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i);
@@ -2043,8 +2037,7 @@ void
Gicv3CPUInterface::virtualIncrementEOICount()
{
// Increment the EOICOUNT field in ICH_HCR_EL2
ArmISA::MiscReg ich_hcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
EOI_cout++;
ich_hcr_el2 = insertBits(ich_hcr_el2, 31, 27, EOI_cout);
@@ -2266,8 +2259,7 @@ Gicv3CPUInterface::eoiMaintenanceInterruptStatus(uint32_t * misr)
bool seen_pending = false;
for (int lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
ArmISA::MiscReg lr =
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
if ((lr & (ICH_LR_EL2_STATE_MASK | ICH_LR_EL2_HW | ICH_LR_EL2_EOI)) ==
ICH_LR_EL2_EOI) {
@@ -2285,7 +2277,7 @@ Gicv3CPUInterface::eoiMaintenanceInterruptStatus(uint32_t * misr)
}
if (misr) {
ArmISA::MiscReg ich_hcr_el2 =
RegVal ich_hcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
if (valid_count < 2 && (ich_hcr_el2 & ICH_HCR_EL2_UIE)) {
@@ -2313,10 +2305,8 @@ Gicv3CPUInterface::maintenanceInterruptStatus()
uint32_t value = 0;
/* Scan list registers and fill in the U, NP and EOI bits */
eoiMaintenanceInterruptStatus(&value);
ArmISA::MiscReg ich_hcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
ArmISA::MiscReg ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
if (ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
value |= ICH_MISR_EL2_LRENP;

4
src/dev/arm/gic_v3_cpu_interface.hh
View File

@@ -252,8 +252,8 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
void init();
void initState();
ArmISA::MiscReg readMiscReg(int misc_reg) override;
void setMiscReg(int misc_reg, ArmISA::MiscReg val) override;
RegVal readMiscReg(int misc_reg) override;
void setMiscReg(int misc_reg, RegVal val) override;
void update();
void virtualUpdate();