Some platforms are not GICv4 compatible, therefore we need to make sure
the stride between redistributors is configurable:
2 frames of 64KiB for GICv3 => a stride of 128KiB
4 frames of 64KiB for GICv4 => a stride of 256KiB
We detect this at runtime by reading the GICD_PIDR2.ArchRev bitfield
This is 3 for GICv3 and 4 for GICv4.
Note: other software projects [1] rely on a different check, mainly
reading the GICR_TYPER.VLPIS bit
We diverge from this behaviour as VLPIS are not implemented and we do
not want to incorrectly report this to the probing software.
We should move to VLPIS once they get implemented
[1]: https://github.com/torvalds/linux/blob/\
107c948d1d3e61d10aee9d0f7c3d81bbee9842af/\
drivers/irqchip/irq-gic-v3.c#L864
Change-Id: I7cc554f48cc6a347c03ed80cf2ea320f618a59c2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59394
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Current way of initializing GICv3 in the gem5 bootloader doesn't
work when there is a PE labelled with non-zero Aff1, Aff2 or Aff3
in the MPIDR_EL1 register
(For example in a multi-cluster configuration).
This is because the bootloader is considering Aff0 only
mrs x0, mpidr_el1
// extract the primary CPU.
ldr x1, =0xff00ffffff
and x2, x0, #0xff // use Aff0 as cpuid for now...
With this patch we are solving the issue, by considering
every affinity number. Now the primary cpu is the cpu with
Aff3..Aff0 = 0.
The bootloader was also using Aff0 (stored in x2, see above)
to let every CPU index their own redistributor memory mapped frames.
In this model every secondary CPU was in charge of initializing
their own redistributor registers.
This can't be used anymore as we have a tuple of affinity
numbers now rather than a single flat index.
We are addressing the issue by letting the primary cpu initialize
every redistributor in the system. This is done by iterating
over consecutive frames and by reading GICR_TYPER.Last, which
is set to 1 if the current frame is the last one.
Change-Id: I2bcad286c2282bf1c47618e5391bf1c2e2b27013
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59393
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Before the commit, the bootloader had a hardcoded entry point that it
would jump to.
However, the Linux kernel arm64 v5.8 forced us to change the kernel
entry point because the required memory alignment has changed at:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?h=v5.8&id=cfa7ede20f133cc81cef01dc3a516dda3a9721ee
Therefore the only way to have a single bootloader that boots both
pre-v5.8 and post-v5.8 kernels is to pass that information from gem5
to the bootloader, which we do in this patch via registers.
This approach was already used by the 32-bit bootloader, which passed
that value via r3, and we try to use the same register x3 in 64-bit.
Since we are now passing this information, the this patch also removes
the hardcoding of DTB and cpu-release-addr, and also passes those
values via registers.
We store the cpu-release-addr in x5 as that value appears to have a
function similar to flags_addr, which is used only in 32-bit arm and
gets stored in r5.
This commit renames atags_addr to dtb_addr, since both are mutually
exclusive, and serve a similar purpose, DTB being the newer recommended
approach.
Similarly, flags_addr is renamed to cpu_release_addr, and it is moved
from ArmSystem into ArmFsWorkload, since it is not an intrinsic system
property, and should be together with dtb_addr instead.
Before this commit, flags_addr was being set from FSConfig.py and
configs/example/arm/devices.py to self.realview.realview_io.pio_addr
+ 0x30. This commit moves that logic into RealView.py instead, and
sets the flags address 8 bytes before the start of the DTB address.
JIRA: https://gem5.atlassian.net/browse/GEM5-787
Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35076
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
CNTFRQ_EL0 should be initialised to a uniform value in all cores present
in the system. Previously, this was only done if EL3 was present,
however architecture states CNTFRQ_EL0 may be written from the highest
EL implemented.
This patch moves this initilization outside of the EL3-only one.
Change-Id: Ibaa197de53d531ba898e5137ba4f46a8c9554699
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24683
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
