b860e2039b
In addition to SVE (which was already being enabled by the bootloader) we also enable SME to allow lower ELs to use it. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1289 Change-Id: I7078a80e9a857c7cf91e3c1e52fe3812fa422394 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64341 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
233 lines
8.2 KiB
ArmAsm
233 lines
8.2 KiB
ArmAsm
/*
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* Copyright (c) 2012, 2020, 2022 Arm Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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.text
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.globl _start
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_start:
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/* Save some values initialized by gem5. */
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/* DTB address. */
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mov x21, x0
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/* Kernel entry point. */
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mov x20, x3
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/* cpu-release-addr. */
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mov x22, x5
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/*
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* EL3 initialisation
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*/
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mrs x0, CurrentEL
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cmp x0, #0xc // EL3?
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b.ne start_ns // skip EL3 initialisation
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mov x0, #0x30 // RES1
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orr x0, x0, #(1 << 0) // Non-secure EL1
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orr x0, x0, #(1 << 8) // HVC enable
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orr x0, x0, #(1 << 10) // 64-bit EL2
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orr x0, x0, #(1 << 16) // Disable FEAT_PAuth traps (APK)
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orr x0, x0, #(1 << 17) // Disable FEAT_PAuth traps (API)
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msr scr_el3, x0
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mov x0, #(1 << 8) // Disable SVE trap to EL3
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orr x0, x0, #(1 << 12) // Disable SME trap to EL3
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msr cptr_el3, x0 // Disable copro. traps to EL3
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/*
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* Check for the primary CPU to avoid a race on the distributor
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* registers.
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*/
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mrs x0, mpidr_el1
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// ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
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// Test the the MPIDR_EL1 register against 0xff00ffffff to
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// extract the primary CPU.
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ldr x1, =0xff00ffffff
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#ifdef GICV3
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tst x0, x1 // check for cpuid==zero
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b.ne 3f // secondary CPU
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ldr x1, =GIC_DIST_BASE // GICD_CTLR
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mov w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S
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str w0, [x1]
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mov x2, #0xffe8
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ldr w2, [x1, x2] // GICD_PIDR2
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and w3, w2, #0xf0 // GICD_PIDR2.Read ArchRev
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cmp w3, #0x30 // Check if GICv3
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mov w4, #0x20000 // 128KiB redistributor stride
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mov w5, #0x40000 // 256KiB redistributor stride
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csel w2, w4, w5, eq // Select the correct redistributor stride
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ldr x1, =GIC_REDIST_BASE
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mov w0, #~0 // Grp1 interrupts
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1: ldr w3, [x1, #0x14] // GICR_WAKER
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and w3, w3, #~0x2 // Setting GICR_WAKER.ProcessorSleep to 0
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str w3, [x1, #0x14]
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dsb sy
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2: ldr w3, [x1, #0x14] // Re-reading GICR_WAKER
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ands w3, w3, #0x4 // Checking GICR_WAKER.ChildrenAsleep
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b.ne 2b // Keep reading GICR_WAKER.ChildrenAsleep until awake
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add x5, x1, #0x10000 // SGI base
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str w0, [x5, #0x80] // GICR_IGROUPR0
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ldr w4, [x1, #0x8] // GICR_TYPER
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add x1, x1, x2 // Point to next redistributor
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// Check GICR_TYPER.Last, which is set to 1
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// if this is the last redistributor
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ands w4, w4, #0x10
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b.eq 1b // Branch back if not last redistributor
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ldr x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR
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str w0, [x1], #4
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str w0, [x1], #4
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str w0, [x1], #4
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/* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */
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3: mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3
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orr x10, x10, #0xf // enable 0xf
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msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3
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isb
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mov x0, #1
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msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable
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msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable
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#else
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tst x0, x1 // check for cpuid==zero
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b.ne 1f // secondary CPU
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ldr x1, =GIC_DIST_BASE // GICD_CTLR
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mov w0, #3 // EnableGrp0 | EnableGrp1
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str w0, [x1]
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1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR
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mov w0, #~0 // Grp1 interrupts
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str w0, [x1], #4
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b.ne 2f // Only local interrupts for secondary CPUs
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str w0, [x1], #4
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str w0, [x1], #4
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2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
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ldr w0, [x1]
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mov w0, #3 // EnableGrp0 | EnableGrp1
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str w0, [x1]
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mov w0, #1 << 7 // allow NS access to GICC_PMR
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str w0, [x1, #4] // GICC_PMR
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#endif
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msr sctlr_el2, xzr
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/*
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* Prepare the switch to the EL2_SP1 mode from EL3
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*/
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ldr x0, =start_ns // Return after mode switch
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mov x1, #0x3c9 // EL2_SP1 | D | A | I | F
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msr elr_el3, x0
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msr spsr_el3, x1
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eret
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start_ns:
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/*
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* Kernel parameters
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*/
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mov x0, xzr
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mov x1, xzr
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mov x2, xzr
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mov x3, xzr
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mrs x4, mpidr_el1
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// ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
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// Test the the MPIDR_EL1 register against 0xff00ffffff to
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// extract the primary CPU.
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ldr x1, =0xff00ffffff
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tst x4, x1 // check for cpuid==zero
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mov x1, xzr // load previous 'xzr' value back to x1
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b.eq 2f // secondary CPU
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/*
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* Secondary CPUs
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*/
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1: wfe
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/* The Linux kernel v5.8 and older writes the entry point address
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* of the secondary CPUs to this address, and does a SEV, waking up
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* the secondary CPUs.
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*
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* gem5 informs the kernel the desired address via cpu-release-addr
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* of the DTB.
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*
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* When this is first reached immediately after the bootloader starts,
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* the value at that address must be 0, which is the default memory
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* value set by gem5 for otherwise uninitialized memory, leading to
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* WFE.
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*/
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ldr x4, [x22]
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cbz x4, 1b
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br x4 // branch to the given address
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2:
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/*
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* UART initialisation (38400 8N1)
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*/
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ldr x4, =UART_BASE // UART base
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mov w5, #0x10 // ibrd
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str w5, [x4, #0x24]
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mov w5, #0xc300
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orr w5, w5, #0x0001 // cr
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str w5, [x4, #0x30]
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/*
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* CLCD output site MB
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*/
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ldr x4, =SYSREGS_BASE
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ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB
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str wzr, [x4, #0xa0] // V2M_SYS_CFGDATA
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str w5, [x4, #0xa4] // V2M_SYS_CFGCTRL
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/*
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* Primary CPU
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*/
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// The kernel boot protocol specifies that the DTB address is placed
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// in x0.
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// https://github.com/torvalds/linux/blob/v5.7/Documentation/arm64/
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// booting.rst#4-call-the-kernel-image
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mov x0, x21
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// Jump into the kernel entry point.
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br x20
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.ltorg
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.org 0x200
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