This stat is only incremented by Alpha. Also move the _hwrei into the Alpha
stats object since it's the class that actually sets up and maintains that
value and it probably should have been there all along.
Change-Id: Ibd038a33230c01432c160490926d8e1e55f8ccb0
Reviewed-on: https://gem5-review.googlesource.com/4601
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
When different sizes were set for the choice and global saturation
counter (e.g. ex5_big), the threshold calculation used the wrong
size. Thus the branch predictor always predicted "not taken" for
choice > global.
Change-Id: I076549ff1482e2280cef24a0d16b7bb2122d4110
Reviewed-on: https://gem5-review.googlesource.com/4560
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
When writing a bitmask of counters to PMSWINC, the PMU currently
increments the corresponding counters regardless of what they are
configured to count. According to the ARM ARM (D5.10.4), counters
should only be updated if they have been configured to count
software events (event type 0).
Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4285
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
PyBind normally casts integers returned from the C to long in
Python. This is normally fine since long in most cases behaves just
like an int. However, when passing the return value from getcode() to
sys.exit, unexpected behavior ensues. Due to the way the function is
defined, any type other than int (with the exception of None) will be
treated as an error and be equivalent to sys.exit(1).
Since we frequently use the sys.exit(event.getCode()) pattern, we need
to ensure that the function returns an integer. This change adds an
explicit type conversion to a Python integer in the wrapper code.
Change-Id: I73d6b881025064afa2b2e6eb4512fa2a4b0a87da
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4280
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Joe Gross <joe.gross@amd.com>
A condition can be specified which will tell the decoder whether to return
the instruction being requested, or, if the condition fails, UD2.
Change-Id: I0f1c075deb10754ce1dd88be1726a196294e41fd
Reviewed-on: https://gem5-review.googlesource.com/4580
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
The error message says an IDE controller can support at most 4 disks, but the
check would fail if there were more than 3 disks.
Change-Id: Ic7d5d8c941fe2580da43019f53991377d4727bb9
Reviewed-on: https://gem5-review.googlesource.com/4460
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The change "config: Change mem_range attribute naming in ARM
SimpleSystem" modified the SimpleSystem class to be compatible with
the MemConfig utility script. While doing so, the way we report the
memory ranges supported by the system changed, which broke the bL
example configration. This changeset introduces the necessary changes
to make the script work again.
Change-Id: I789987950ff04b6c5ae1c8b807355bcba34f6b3c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4380
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The ARM example configs used to rely on CPU aliases for the
AtomicSimpleCPU and KVM when configuring clusters. This broken when
support for CPU aliases was removed ('config: Remove support for CPU
aliases.'). This change updates the config scripts to use the full
class names instead.
Change-Id: If36c46207f39ca1897ecf77d9588f1c059819e63
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4360
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
When asynchronous IO fails, gem5 currently just says it failed and quits, and
doesn't give any more information about which step failed, or what
specifically about it failed.
This change adds two helpers which will attempt the fcntl, check for error
conditions, and in the event of a failure, include a message describing the
error code and what the arguments to fcntl were.
Change-Id: I316478172ab2aefd3788279dbc12744791385cd5
Reviewed-on: https://gem5-review.googlesource.com/4320
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Teach the style checker about common headers living in gem5/. These
should be included after any global library headers (e.g., C headers
or STL headers), but before the normal gem5 headers.
Change-Id: I322f841420e361c16314be8fa4cbd1e86d2bfa9f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4300
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The header file with C declarations for m5ops is sometimes needed by
code outside of the util/m5 directory. Move this file to the shared
include directory and factor out flags to a generic asm header. Note
that applications that need to call m5ops still need to link with
libm5.a or implement their own trampolines.
Change-Id: I36a3f459ed71593e38b869dc2b1302c810f92276
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4265
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The header file m5ops.h contains a list of constants that should be
shared between the simulator and utilities. Move this header file to a
new top-level directory for shared files and rename constants to make
them suitable for inclusion in the main simulator.
The structure of the shared include directory is as follows:
include/gem5: Files that can be included from C code.
include/gem5/asm: Files that can be included from assembly code.
asm/generic/: Files that aren't guest ISA specific
asm/${isa}/: Files that are guest ISA specific
Change-Id: I1aa511057bcaa80cc2d566109ff26581558c4a41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jose Marinho <jose.marinho@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
ISA devices typically run in the device event queue. Previously, we
assumed that devices would perform their own EQ migrations as
needed. This isn't ideal since it means we have different conventions
for IO devices and ISA devices. Switch to doing migrations in the KVM
CPU instead to make the behavior consistent.
Change-Id: I33b74480fb2126b0786dbdbfdcfa86083384250c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4288
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The VM's event queue is normally used for devices in multi-core KVM
mode. Add a helper method, BaseKvmCPU::deviceEventQueue(), to access
this queue. This makes the intention of code migrating to device event
queues clearer.
Change-Id: Ifb10f553a6d7445c8d562f658cf9d0b1f4c577ff
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4287
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The KVM CPU sometimes needs to access devices when drain() is
called. This typically happens on ARM when synchronizing devices that
use the system register interface. When called from drain(), the event
queue isn't locked since drain is called from the outside when the
simulator isn't servicing any events. In such cases, performing a
migration to the device's queue will unlock a mutex that isn't
locked. This typically results in a deadlock when resuming the system
since the lock will be in an undefined state.
Change-Id: Ibdcc2e034e916a929124f297e72aae306cf66728
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4286
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Old ARM systems used to pass the machine type in the ATAGS list passed
to the kernel. This has been largely deprecated by the introduction of
device trees. Switch to the DTOnly machine type by default in gem5
since all new platforms and kernel will require this behavior.
Change-Id: Icfd085e4862863b4ef495566bfddbd11591866c3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4260
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
The CpuConfig helper currently assumes that all timing models live in
the cores.arm package. This ignores the potential mismatch between the
target ISA and the ISA assumptions made by the timing models.
Instead of unconditionally listing all CPU models in cores.arm, list
timing models from cores.generic and cores.${TARGET_ISA}. This ensures
that the listed timing models support the ISA that gem5 is targeting.
Change-Id: If6235af2118889638f56ac4151003f38edfe9485
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3947
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
The High-Performance In-order (HPI) CPU timing model is tuned to be
representative of a modern in-order ARMv8-A implementation. The HPI
core and its supporting simulation scripts, namely starter_se.py and
starter_fs.py (under /configs/example/arm/) are part of the ARM
Research Starter Kit on System Modeling. More information can be found
at: http://www.arm.com/ResearchEnablement/SystemModeling
Change-Id: I124bd06ba42d20abff09d447542b031d17eabe22
Signed-off-by: Ashkan Tousi <ashkan.tousimojarad@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4201
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
MemConfig.config() expects memory ranges to be defined in a particular
way. This patch changes the naming of the mem_range attribute in
SympleSystem to enable use of MemConfig for configuring the memory.
Change-Id: I4964c136e53a99c69ff5e086cacb929aa435168d
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4200
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Assign different pids to the different commands specified with the "--cmd"
flag to configs/example/se.py
Without this change, the following command line triggers
a "fatal: _pid 100 is already used" error:
command=$PWD/tests/test-progs/hello/bin/arm/linux/hello
./build/ARM/gem5.opt configs/example/se.py -n 2 -c "$command;$command"
Change-Id: If6f726481eb196d4f42680b6aa46364fce4190ed
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/4160
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
The introduction of a new vector register class broke rename in the O3
CPU due to an unhandled register class in
DefaultRename<Impl>::renameSrcRegs(). This patch fixes adds the
necessary handling to avoid a panic when the vector register file is
used.
Change-Id: Ie380ab35ec4a151db15402f25b25b58931ee0581
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4140
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Checkpointing a system with out-of-order CPUs might get stuck if
one of the CPUs has been put to sleep. The quiesce instruction
cannot get drained hence checkpointing never finishes.
This commit resolves that by activating all suspended thread
contexts when draining the system.
Change-Id: I817ab1672b4ead777bd8e12a0445829481c46fdc
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3970
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This fixes the function call to clone in syscall_emul.hh where
the x86 version should be called before the base implementation
of clone.
Change-Id: Iccd2f680ff6e3a5536037d688a80ab3f236bbd98
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3902
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
To make it clearer what the register indices are for the semantically
meaningful registers defined by src/arch/riscv/registers.hh, the
constants that were defined using other constants were changed to use
the literal values of those constants. This also removes the need to
use the M5_VAR_USED attribute.
Change-Id: I7cccbe45d3d820deb5149a5925415735f6ae2e61
Reviewed-on: https://gem5-review.googlesource.com/4080
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
When both the C and C++ versions are visible, the compiler will complain that
it doesn't know which one to use. By specifying the std namespace, it will
know to use the C++ version.
Change-Id: Ie1bbe1d95eadbad9644b4915c21f924d7d5c0b22
Reviewed-on: https://gem5-review.googlesource.com/4060
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
This patch updates the binaries and results for hello and insttest
regressions using the compressed extension.
Change-Id: I3d8f2248f490521d3e0dc05c48735cab82b1b04e
Reviewed-on: https://gem5-review.googlesource.com/4042
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen. The rest of these
assertions will be changed in a later patch.
[Remove commented-out debugging line and add clarifying comment to
registerName in utility.hh.]
Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
Reviewed-on: https://gem5-review.googlesource.com/4041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Three of the constants defined in arch/riscv/registers.hh
(ReturnValueReg, SyscallNumReg, and SyscallPseudoReturnReg) may cause
the compiler to warn that they are unused, which results in an error.
This patch adds M5_VAR_USED attributes to them to stop this.
Change-Id: Ie6389a55e8ffb3d003a47d02e76bdf9fb5219457
Reviewed-on: https://gem5-review.googlesource.com/4040
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
The LDM instruction that loads to the PC causes a branch to the
instruction. In ARMv5T+ the branch can interswitch Thumb and ARM modes.
The interswitch is broken prior to this commit, with LDM to the PC
ignoring the switch.
Change-Id: I6aad073206743f3435c9923e3e2218bfe32c7e05
Reviewed-on: https://gem5-review.googlesource.com/3520
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
