Commit Graph

93 Commits

Author SHA1 Message Date
Gabe Black
e4be93b55f sim: Add some helpers for setting up Signal*Ports in python.
The only difference between these types in python are the compatibility
strings which restrict what can connect to what. For ports which are
generally useful like interrupts or resets, they should have port types
with special names and even more restrictive compatibility. For other
ports which are one off signals between components, that would be
overkill, and these helpers will let you make a signal port which is
only restricted to ports which carry the same type of data.

The helpers are intended to look similar to their C++ counterpart
templates, and are functions which take a type signature as a string
as their argument, and return a class which is specialized to use that
type signature. The class itself can be stored, or used immediately.

foo = SignalSourcePort('bool')('A port for the foo signal')

Change-Id: If6359b2c69f34ff775cd9aa01272ac487db08bf7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67511
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
2023-02-02 01:01:56 +00:00
Gabe Black
a13e3debed misc: Stop excluding code when building the NULL ISA.
The BaseCPU needs a little extra hacking because it tries to create
default objects based on what the ISA is. If the ISA isn't recognized,
then the types will be set to None, and some extra checks have been
added as the type is set up.

Change-Id: Ia3cae313e1a96a953d2316d9192f41a8fd28c141
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62195
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-08-20 07:30:07 +00:00
Giacomo Travaglini
f8589a4719 sim, arch-riscv: Remove Fault debug flag
There is already a Faults debug flag used by Arm and X86 so
having both Fault and Faults is highly confusing

Change-Id: Id5c17f19b51c6257dfc470d07ba050a9de7a9db3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59152
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-04-28 08:52:49 +00:00
Gabe Black
e6c0ba97db scons: Put all config variables in an env['CONF'] sub-dict.
This makes what are configuration and what are internal SCons variables
explicit and separate, and makes it unnecessary to call out what
variables to export to C++.

These variables will also be plumbed into and out of kconfiglib in later
changes.

Change-Id: Iaf5e098d7404af06285c421dbdf8ef4171b3f001
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56892
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-28 20:31:21 +00:00
Gabe Black
9df4159456 sim: Add some helpers for working with values in buffers.
This change adds helpers to get and set values from byte buffers of
variable size, and to print them. It also provides a helper to print a
buffer of bytes.

Change-Id: I23210505f99488a901bed244ffc70ef4736470d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57149
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-26 09:56:26 +00:00
Daniel R. Carvalho
f65e370e39 sim,tests: Add a tag for drain-related files
This tag can be used to determine which files are needed
when sim/drain.hh is included in a header file. For
example, when declaring a unit test, this tag makes
the SConscript declaration much simpler.

Change-Id: Ie8a44291a0408090ffbb5b078582d3c5c8d1fd55
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44108
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-09 10:24:54 +00:00
Daniel R. Carvalho
0ea570c8a1 sim,tests: Add a tag for gem5 events
This tag can be used to determine which files are needed
when sim/eventq.hh is included in a header file. For
example, when declaring a unit test, this tag makes
the SConscript declaration much simpler.

Change-Id: If68ddf94975dbe9f7121fefb6051a8bbaca19c4b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44107
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-09 10:24:54 +00:00
Daniel R. Carvalho
a4195d3ed1 sim,tests: Add unit test for Globals
Add a unit test for sim/globals.

Change-Id: Ia47e750df4cbdb91a0ab0498819f4e3451d74830
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43593
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-09 10:24:54 +00:00
Gabe Black
1c233ee9d2 scons: Add sim_object and enums arguments to SimObject().
This will explicitly declare what SimObject and Enum types need to be set
up in C++, which will make importing all the SimObject modules during
the setup phase of SCons uneccessary.

Change-Id: Id2d7603daf33b236ceaa0789e2f089f589d34e62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49406
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 08:01:23 +00:00
Daniel R. Carvalho
cbffe30e64 sim,tests: Add unit test for sim/serialize.hh
Add a unit test for sim/serialize.hh.

==Bugs==
arrayParamIn cannot parse strings with spaces. Since spaces
are used as delimiters, strings containing spaces are parsed
as multiple entries of the array. The test that checks for
this has been disabled.

==Unexpected Behavior==
Serialization has an unexpected behavior when returning to
previous scopes. For example,

  ...
  SCS scs(cpt, "S1")
  paramOut(cpt, "param1", integer1)
  {
    SCS scs_2(cpt, "S2")
    paramOut(cpt, "param2", integer2)
  }
  paramOut(cpt, "param3", integer3)

will generate the output:
  ...
  [S1]
    param1=1
  [S2]
    param2=2
    param3=3

But the user might expect:
  ...
  [S1]
    param1=1
  [S2]
    param2=2
  [S1]
    param3=3

==Incovenient Behavior==
arrayParamIn with a std::array parameter is slightly
incovenient, since the raw data pointer must be extracted.
It may be worth it to add a template specialization.

==Not Tested==
paramInImpl is not being directly tested because it should
not be used as an external API - paramIn and optParamIn
should be used instead.

arrayParamIn with an InsertIterator parameter is not being
directly tested because the other versions should be used
instead.

Change-Id: If0c8f045aa317790d5fcb32e48629b113b62efc5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41337
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-22 05:31:01 +00:00
Daniel R. Carvalho
df928b36f8 sim,tests: Add unit test for sim/serialize_handlers
Add a GTest for the functionality of sim/serialize_handlers.hh.

Change-Id: I1128c7adb12a3c7d091e26db13733ba45e1e61fe
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38776
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-22 05:31:01 +00:00
Daniel R. Carvalho
94d44ada63 sim: Add unit test for sim/port
Add a unit test for sim/port.

The fact that binding a port does not automatically
bind its peer is error-prone, and should likely be
revisited in the future.

Change-Id: Iee91fc9bfa80a527d9a1902529722833b061dec9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43003
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-16 10:50:26 +00:00
Daniel R. Carvalho
7f5bd15f51 base: Add unit test for base/trace.hh
Add an unit test for base/trace.hh.

Marked the source files needed for tracing with a 'gem5 trace'
tag.

Change-Id: Ib1e17de3c772146596a26a2ce5aa7a6310bf7938
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41336
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-16 10:50:26 +00:00
Daniel R. Carvalho
19c7429520 sim,util: Remove event dependencies from serialize.hh
With this change serialize.hh is no longer responsible
for the (un)serialization of events. As a general rule,
rules to (un)serialize non-basic types should be defined
at the file that introduces that type. Therefore,
(UN)SERIALIZE_EVENT have been moved to eventq.hh.

Globals has a single instance which must be serialized
and unserialized. Instead of having a stray global
variable handled by Serialization, we pass its management
to Root. As a side effect, Globals is assigned its own
files: sim/globals.(cc/hh).

Finally, 'unserializeGlobals()' is removed, so that
Root can fully handle Globals' serialization. This
breaks checkpoint compatibility, so a checkpoint
upgrader is added.

Change-Id: I9c8e57306f83f9cc30ab2b745a4972755191bec4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43586
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-16 10:50:26 +00:00
Michael LeBeane
e4537dfbba sim: Add pool specific allocators to SE mode
The System object supports multiple memory pools but there is currently
no way to specify which pool to allocate from in SE mode.  This patch
adds a optional poolID argument to the allocation functions.

Change-Id: I1c732f28905f3b3875adee5f2b0d9abb39a6c5d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42215
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-22 20:01:33 +00:00
Gabe Black
2f424f6a13 sim: Track ThreadContext-s in the Workload object.
Change-Id: I00bf9fa36d3993f55d41e50196ad8a89a3d506c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44616
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
2021-04-20 07:44:19 +00:00
Daniel R. Carvalho
3bb86373ee sim: Move cur tick to its own files
When declared within sim/core.hh, unit tests that use the
current tick would have to unnecessarily include many other
extra files.

Change-Id: Ib4348312afb90765edb4f94c80785df1275b2004
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39835
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-02-03 01:12:27 +00:00
Andreas Sandberg
b9c7dae41f sim, stats: Move global stats to Root
Global stats are currently exposed using the legacy stat system (i.e.,
without a parent group). This change moves global stats from
stat_control.cc to a group that gets exported from the Root object.

The implementation adds the Root::Stats class which has a single
global instance. This instance is exposed to the rest of the simulator
using the global rootStats symbol. The intention is that objects that
need global statistics in formulas access them through the rootStats
object.

The global names simSeconds, simTicks, simFreq, and hostSeconds are
now references to their respective members in the rootStats object.

Change-Id: I267b5244a0bcca93dd2dcf03388e7085bdd79c9e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35616
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-09 09:56:52 +00:00
Gabe Black
3293926413 sim: Create a Workload object for SE mode.
The workload object is still optional for the sake of compatibility,
even though it probably shouldn't be in the long term. If a simulation
is just a collection of components with nothing in particular running on
it, for instance driven by a traffic generator, should it even have a
System object in the first place?

Change-Id: I8bcda72bdfa3730248226fb62f0bba9a83243d95
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33278
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-09-20 07:26:22 +00:00
Gabe Black
cac49d4e47 arch,cpu,sim: Get rid of the microcode ROM stub code.
This code, including a switching header file, is no longer necessary
because ROM based microops are now handled by the decoder itself.

Change-Id: Ie3ea4a7371dec22993ede80e2acd1df7cd1ecf59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32899
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-08-25 12:41:30 +00:00
Ciro Santilli
aa219dba7a sim-se: split futex_map.cc into header and source files
To speed up development when modifying the implementation.

Change-Id: I1b3c67c86f8faa38ed81a538521b08e256d21a5a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29775
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-08-10 08:52:03 +00:00
Gabe Black
536ea331b0 sim: Add a ProxyPtr test.
Change-Id: If71cc374030a5ef0dab62d351bc83960ff509af7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29401
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-07-17 01:01:13 +00:00
Anouk Van Laer
cc2f48ccfc sim-power: Addition of PowerDomains
PowerDomains group multiple objects together to regulate their power
state. There are 2 types of objects in a PowerDomain: leaders and
followers. The power state of a PowerDomain is the most performant
power state of any of the leaders. The power state of the followers is
determined by the power state of the PowerDomain they belong to: they
need to be in a power state which is more or equally performant to the
power state of the PowerDomain.

Leaders can be ClockedObjects or other PowerDomains. Followers can
only be ClockedObjects. PowerDomains can be be nested but a
PowerDomain can only be a leader of another PowerDomain, NOT a
follower. PowerDomains are not present in the hierarchy by default,
the user needs to create and configure them in the configuration file.

The user can add an hierachy by setting the led_by parameter. gem5
will then create leaders and followers for each domain and calculate
the allowed power states for the domain.

Objects in a PowerDomain need to have at least the ON state in the
possible_states.

An example of a powerDomain config is:

pd = PowerDomain()
cpu0 = BaseCPU()
cpu1 = BaseCPU()
shared_cache = BaseCache()
cache.power_state.led_by = pd
pd.led_by = [cpu0, cpu1]

This will create a PowerDomain, where the CPUs determine their own
power states and the shared cache (via the PowerDomain) follows those
power states (when possible).

Change-Id: I4c4cd01f06d45476c6e0fb2afeb778613733e2ff
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28051
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:03:31 +00:00
Anouk Van Laer
818961969a sim-power: Creation of PowerState class
This commit does not make any functional changes but just rearranges
the existing code with regard to the power states. Previously, all
code regarding power states was in the ClockedObjects. However, it
seems more logical and cleaner to move this code into a separate
class, called PowerState. The PowerState is a now SimObject. Every
ClockedObject has a PowerState but this patch also allows for objects
with PowerState which are not ClockedObjects.

Change-Id: Id2db86dc14f140dc9d0912a8a7de237b9df9120d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28049
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-29 21:03:31 +00:00
Gabe Black
2d4829657d configs,arch,sim: Move fixFuncEventAddr into the Workload class.
This is specialized per arch, and the Workload class is the only thing
actually using it. It doesn't make any sense to dispatch those calls
over to the System object, especially since that was, in most cases,
the only reason an ISA specific system class even still existed.

After this change, only ARM still has an architecture specific System
class.

Change-Id: I81b6c4db14b612bff8840157cfc56393370095e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24287
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-04-22 00:22:28 +00:00
Gabe Black
da4f5726be arch,sim,kern,dev,cpu: Create a Workload SimObject.
This generalized Workload SimObject is not geared towards FS or SE
simulations, although currently it's only used in FS. This gets rid
of the ARM specific highestELIs64 property (from the workload, not the
system) and replaces it with a generic getArch.

The old globally accessible kernel symtab has been replaced with a
symtab accessor which takes a ThreadContext *. The parameter isn't used
for anything for now, but in cases where there might be multiple
symbol tables to choose from (kernel vs. current user space?) the
method will now be able to distinguish which to use. This also makes
it possible for the workload to manage its symbol table with whatever
policy makes sense for it.

That method returns a const SymbolTable * since most of the time the
symbol table doesn't need to be modified. In the one case where an
external entity needs to modify the table, two pseudo instructions,
the table to modify isn't necessarily the one that's currently active.
For instance, the pseudo instruction will likely execute in user space,
but might be intended to add a symbol to the kernel in case something
like a module was loaded.

To support that usage, the workload has a generic "insertSymbol" method
which will insert the symbol in the table that "makes sense". There is
a lot of ambiguity what that means, but it's no less ambiguous than
today where we're only saved by the fact that there is generally only
one active symbol table to worry about.

This change also introduces a KernelWorkload SimObject class which
inherits from Workload and adds in kernel related members for cases
where the kernel is specified in the config and loaded by gem5 itself.
That's the common case, but the base Workload class would be used
directly when, for instance, doing a baremetal simulation or if the
kernel is loaded by software within the simulation as is the case for
SPARC FS.

Because a given architecture specific workload class needs to inherit
from either Workload or KernelWorkload, this change removes the
ability to boot ARM without a kernel. This ability should be restored
in the future.

To make having or not having a kernel more flexible, the kernel
specific members of the KernelWorkload should be factored out into
their own object which can then be attached to a workload through a
(potentially unused) property rather than inheritance.

Change-Id: Idf72615260266d7b4478d20d4035ed5a1e7aa241
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24283
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-22 00:22:28 +00:00
Matthew Poremba
56ee199b3d sim-se: Extend MemState API to use VMAs
Extend the MemState API to handle tracking dynamically sized memory
regions of a Process class which may be added, moved, removed, or
change in size during the course of simulation. This utilizes the
virtual memory areas (VMA) class to track individual regions and
provides a fixup method to handle physical page allocation in case of
a page fault. This allows for lazy allocation of the stack, heap, and
mmap regions of memory.

Change-Id: I3ef10657e5f8e8f0e328bdf0aa15a27b1dde39bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25483
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-03-25 15:42:45 +00:00
Gabe Black
db7f6a5fa8 sim: Get rid of the Arguments class.
This class read arguments using the arch specific getArgument function
and then presented the arguments as an array. The problem with that
approach is that it's not possible to tell where different arguments
are without knowing the types of previous arguments, and not all
arguments can be simply represented as a native sized integer.

This class has been phased out and is no longer needed.

Change-Id: Ibb4c529fe8c51fd0ae15ed3b6ea30543ad9c23e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24115
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2020-03-20 10:04:18 +00:00
Matthew Poremba
1566e47017 sim-se: Implement Virtual Memory Area API
Virtual memory areas are used to track regions of memory which may
change over the course of execution, such as heap, stack, and mmap. It
is a high-level mimicry of Linux' memory management. VMAs are intended
to be used to support lazy allocation of physical pages to valid VMAs
as the virtual addresses are touched. Lazy allocation increases speed
of simulation for SE mode processes which, for example, mmap large
files.

The VMAs can also be queried to generate a map of the process' memory
which is used in some libraries such as pthreads.

This changeset only adds APIs for virtual memory areas. These are used
in a subsequent changeset.

Change-Id: Ibbdce5be79a95e3231d2e1c9ee8f397b4503f0fb
Signed-off-by: Brandon Potter <Brandon.Potter@amd.com>
Signed-off-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25365
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-19 14:24:19 +00:00
Gabe Black
73fdc2eb57 config,arch,cpu,kern,sim: Extract kernel information from System.
Information about what kernel to load and how to load it was built
into the System object and its subclasses. That overloaded the System
object and made it responsible for too many things, and also was
somewhat awkward when working with SE mode which doesn't have a kernel.

This change extracts the kernel and information related to it from the
System object and puts into into a OsKernel or Workload object.
Currently the idea of a "Workload" to run and a kernel are a bit
muddled, an unfortunate carry-over from the original code. It's also an
implication of trying not to make too sweeping of a change, and to
minimize the number of times configs need to change, ie avoiding
creating a "kernel" parameter which would shortly thereafter be
renamed to "workload".

In future changes, the ideas of a kernel and a workload will be
disentangled, and workloads will be expanded to include emulated
operating systems which shephard and contain Process-es for syscall
emulation.

This change was originally split into pieces to make reviewing it
easier. Those reviews are here:

https: //gem5-review.googlesource.com/c/public/gem5/+/22243
https: //gem5-review.googlesource.com/c/public/gem5/+/24144
https: //gem5-review.googlesource.com/c/public/gem5/+/24145
https: //gem5-review.googlesource.com/c/public/gem5/+/24146
https: //gem5-review.googlesource.com/c/public/gem5/+/24147
https: //gem5-review.googlesource.com/c/public/gem5/+/24286

Change-Id: Ia3d863db276a023b6a2c7ee7a656d8142ff75589
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26466
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-11 15:57:14 +00:00
Gabe Black
eb40af3bd4 sim: Delete authors lists from files in sim.
Change-Id: I09a6117772c092157bf83701cf853145bb88ccf8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25411
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-18 03:34:31 +00:00
Gabe Black
aabe7e1f69 sim: Add a unit test for the GuestABI mechanism.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I76934d94b4c61570a4ca603388012c65280e2b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23197
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-13 22:44:49 +00:00
Bobby R. Bruce
54909088e7 tests: Added GTests for byteswap.hh
In addition to the test, "#include base/logging.hh" was added to the
"byteswap.hh". It is is required to compile the header.

Added tests ByteswapTest.swap_byte64, ByteswapTest.swap_byte32,
ByteswapTest.swap_byte16, ByteswapTest.swap_byte, ByteswapTest.htog,
and ByteswapTest.gtoh. The file byteswap.hh is mostly templates.

Added test for BigEndianGuest and LittleEndianGuest namespaces.

Change-Id: I8870a55594ed439fe9e1fb333384f73261d1b1b8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22080
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-16 07:25:58 +00:00
Gabe Black
9305bb6e83 arch, sim: Simplify the AuxVector type.
The AuxVector type has a bunch of accessors which just give access to
the underlying variables through references. We might as well just make
those members accessible directly.

Also, the AuxVector doesn't need to handle endianness flips itself. We
can tell the byteswap mechanism how to flip an AuxVector, and let it
handle that for us.

This gets rid of the entire .cc file which was complicated by trying
to both hide the ISA specific endianness translations, and instantiate
templated functions in a .cc.

Change-Id: I433cd61e73e0b067b6d628fba31be4a4ec1c4cf0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18373
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-28 05:16:01 +00:00
David Hashe
54c77aa055 sim-se: add a faux-filesystem
This change introduces the concept of a faux-filesystem.
The faux-filesystem creates a directory structure in m5out
(or whatever output dir the user specifies) where system calls
may be redirected.

This is useful to avoid non-determinism when reading files
with varying path names (e.g., variations from run-to-run if
the simulation is scheduled on a cluster where paths may change).

Also, this changeset allows circumventing host pseudofiles which
have information specific to the host processor (such as cache
hierarchy or processor information). Bypassing host pseudofiles
can be useful when executing runtimes in the absence of an
operating system kernel since runtimes may try to query standard
files (i.e. /proc or /sys) which are not relevant to an
application executing in syscall emulation mode.

Change-Id: I90821b3b403168b904a662fa98b85def1628621c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25 18:11:34 +00:00
Gabe Black
d3d24835bc arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Replace the getMasterPort, getSlavePort, and getEthPort functions
with getPort, and remove extraneous mechanisms that are no longer
necessary.

Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19 10:22:50 +00:00
Gabe Black
993c26938c mem: Move the Port base class into sim.
The Port class is going to be officially used for more than just memory
system connections.

Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15 18:38:35 +00:00
Gabe Black
85168c4e96 scons: Switch from "guards" to "tags" on source files.
Tags are just arbitrary strings which are attached to source files
which mark them as having some property. By default, all source files
have the "gem5 lib" tag added to them which marks them as part of the
gem5 library, the primary component of the gem5 binary but also a
seperable component for use in, for example, system C.

The tags can be completely overridden by setting the "tags" parameter
on Source, etc., functions, and can be augmented by setting "add_tags"
which are tags that will be added, or alternatively additional tags.
It's possible to specify both, in which case the tags will be set to
the union of tags and add_tags. add_tags is supposed to be a way to
add extra tags to the default without actually overriding the default.
Both tags and add_tags can be a list/tuple/etc of tags, or a single
string which will be converted into a set internally.

Other existing tags include:
1. "python" for files that need or are used with python and are
   excluded when the --without-python option is set
2. "main" for the file(s) which implement the gem5 binary's main
   function.
3. The name of a unit test to group its files together.
4. Tags which group source files for partial linking.

By grouping the "tags" into a single parameter instead of taking all
extra parameters as tags, the extra parameters can, in the future, be
passed to the underlying scons environment. Also, the tags are either
present or not. With guards, they could be present and True, present
and False, or not present at all.

Change-Id: I6d0404211a393968df66f7eddfe019897b6573a2
Reviewed-on: https://gem5-review.googlesource.com/5822
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-27 22:08:50 +00:00
Brandon Potter
8b85f950e5 syscall-emul: Adds SE mode signal feature
This changeset adds a simple class definition and a member
in the System object to track signals sent between processes.
The implementation cannot support all signals that might be
sent between processes, but it can support some of the simple
use cases like SIGCHLD.

Change-Id: Id5f95aa60e7f49da1c5b5596fbfa26e729453ac7
Reviewed-on: https://gem5-review.googlesource.com/2267
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-03-09 22:42:45 +00:00
Brandon Potter
d3d983caf9 syscall_emul: [patch 10/22] refactor fdentry and add fdarray class
Several large changes happen in this patch.

The FDEntry class is rewritten so that file descriptors now correspond to
types: 'File' which is normal file-backed file with the file open on the
host machine, 'Pipe' which is a pipe that has been opened on the host machine,
and 'Device' which does not have an open file on the host yet acts as a pseudo
device with which to issue ioctls. Other types which might be added in the
future are directory entries and sockets (off the top of my head).

The FDArray class was create to hold most of the file descriptor handling
that was stuffed into the Process class. It uses shared pointers and
the std::array type to hold the FDEntries mentioned above.

The changes to these two classes needed to be propagated out to the rest
of the code so there were quite a few changes for that. Also, comments were
added where I thought they were needed to help others and extend our
DOxygen coverage.
2016-11-09 14:27:42 -06:00
Brandon Potter
49009f170a syscall_emul: [patch 8/22] refactor process class
Moves aux_vector into its own .hh and .cc files just to get it out of the
already crowded Process files. Arguably, it could stay there, but it's
probably better just to move it and give it files.

The changeset looks ugly around the Process header file, but the goal here is
to move methods and members around so that they're not defined randomly
throughout the entire header file. I expect this is likely one of the reasons
why I several unused variables related to this class. So, the methods are
declared first followed by members. I've tried to aggregate them together
so that similar entries reside near one another.

There are other changes coming to this code so this is by no means the
final product.
2016-11-09 14:27:41 -06:00
Brandon Potter
a928a438b8 style: [patch 3/22] reduce include dependencies in some headers
Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.
2016-11-09 14:27:40 -06:00
Brandon Potter
1ced08c850 syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
The class was crammed into syscall_emul.hh which has tons of forward
declarations and template definitions. To clean it up a bit, moved the
class into separate files and commented the class with doxygen style
comments. Also, provided some encapsulation by adding some accessors and
a mutator.

The syscallreturn.hh file was renamed syscall_return.hh to make it consistent
with other similarly named files in the src/sim directory.

The DPRINTF_SYSCALL macro was moved into its own header file with the
include the Base and Verbose flags as well.

--HG--
rename : src/sim/syscallreturn.hh => src/sim/syscall_return.hh
2016-11-09 14:27:40 -06:00
David Guillen Fandos
7cfb59d6e5 sim: Adding support for power models
This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Change-Id: I76752f9638b6815e229fd74cdcb7721a305cbc4b
2016-06-06 17:16:44 +01:00
David Guillen Fandos
5350879f49 pwr: Add power states to ClockedObject
Add 4 power states to the ClockedObject, provides necessary access
functions to check and update the power state. Default power state
is UNDEFINED, it is responsibility of the respective simulation
model to provide the startup state and any other logic for state
change. Add number of transition stat. Add distribution of time
spent in clock gated state. Add power state residency stat. Add
dump call back function to allow stats update of distribution
and residency stats.

Change-Id: Id086090a2ed720c9fcb37812a3c98f0f724907c6
2016-06-06 17:16:43 +01:00
Andreas Sandberg
fd52a63e24 Revert to 74c1e6513bd0 (sim: Thermal support for Linux) 2016-04-07 10:42:07 +01:00
Andreas Sandberg
be28d96510 Revert power patch sets with unexpected interactions
The following patches had unexpected interactions with the current
upstream code and have been reverted for now:

e07fd01651f3: power: Add support for power models
831c7f2f9e39: power: Low-power idle power state for idle CPUs
4f749e00b667: power: Add power states to ClockedObject

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

--HG--
extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
2016-04-06 19:43:31 +01:00
David Guillen Fandos
f902c0218a power: Add support for power models
This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Finally, the thermal model is updated to use the power usage as input.
2016-04-05 10:52:28 -05:00
Akash Bagdia
3ee4957b49 power: Add power states to ClockedObject
Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.

Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.

Add dump call back function to allow stats update of distribution and residency
stats.
2014-11-18 14:00:48 +00:00
David Guillen Fandos
75c82f1fe3 sim: Adding thermal model support
This patch adds basic thermal support to gem5. It models energy dissipation
through a circuital equivalent, which allows us to use RC networks.
This lays down the basic infrastructure to do so, but it does not "work" due
to the lack of power models. For now some hardcoded number is used as a PoC.
The solver is embedded in the patch.
2015-05-12 10:26:47 +01:00