Commit Graph

6 Commits

Author SHA1 Message Date
Harshil Patel
5288dbbf90 mem: Updated bytesRead and bytesWritten stat (#705)
- The bytesRead and bytesWritten stat had duplicate names. Updated
bytesRead and bytesWritten for dram_interface and nvm_interface

Change-Id: I7658e8a0d12ef6b95819bcafa52a85424f01ac76
2023-12-21 10:21:40 -08:00
Ayaz Akram
32df25e426 mem: HBMCtrl changes to allow PC data buses to be in different states
This change updates the HBMCtrl such that both pseudo channels
can be in separate states (read or write) at the same time. In
addition, the controller queues are now always split in two
halves for both pseudo channels.

Change-Id: Ifb599e611ad99f6c511baaf245bad2b5c9210a86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65491
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2023-05-26 20:08:00 +00:00
Ayaz Akram
09b3ff5187 mem: Fix the respondEvent check in DRAM interface
This change fixes the respondEvent schedule check
in DRAM interface to make sure that the correct respondEvent
is checked for a given pseudo channel.

Change-Id: Ie5edf48db9f6cf2e7ee4cafe7b774441464d77a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61629
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-08-28 01:20:43 +00:00
Ayaz Akram
feceff7723 mem: Support for separate tRCD and tCL for reads/writes
HBM2 has asynchronous read/write timings (tRCD, tCL). This change
updates dram interface in gem5 to allow using separate values of
tRCD and tCL for reads and writes.

Change-Id: I56bfa9519cedad89cc2d4c163efc7126f609f15a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59733
Reviewed-by: Wendy Elsasser <welsasser@rambus.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-06 18:31:06 +00:00
Ayaz Akram
60317f99fe mem: Add an HBM memory controller
This change adds an hbm memory controller in gem5,
which is capable of controlling two hbm memory interfaces
(two pseudo channels). HBMCtrl inherits from MemCtrl
and tries to reuse most of the MemCtrl functions for two
different dram interfaces. Morever, a notion of pseudo
channel is added in the memory interface itself, to make
sure that the scheduling decisions in any interface are
based on the pkts for that pseudo channel only. Also, the
command bandwidth checks are divided into row and column
commands, which are shared by both pseudo channels.

Change-Id: Ie2ee8183d0f7f744aff2ed05cabc75fec3ea2171
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59732
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Wendy Elsasser <welsasser@rambus.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-06 18:31:06 +00:00
Maryam Babaie
c7c11c5661 mem: splitting dram and nvm interfaces into separate files
This change primarily splits the dram and nvm interfaces
into separate files. And also updates the interfaces so that
they can be handled in a more general way by the controller.
For example, both interfaces now override a virtual isBusy()
function defined in the mem_interface.

Change-Id: Id98bf0be3836a4b6245d5dea1b8fad0a60ce299a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59730
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2022-06-06 18:31:06 +00:00