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mem: splitting dram and nvm interfaces into separate files

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This change primarily splits the dram and nvm interfaces
into separate files. And also updates the interfaces so that
they can be handled in a more general way by the controller.
For example, both interfaces now override a virtual isBusy()
function defined in the mem_interface.

Change-Id: Id98bf0be3836a4b6245d5dea1b8fad0a60ce299a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59730
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Maryam Babaie
2022-05-04 10:39:32 -07:00
committed by Bobby Bruce
parent f876e60bc2
commit c7c11c5661
11 changed files with 3960 additions and 3530 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mem/DRAMInterface.py
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@@ -48,7 +48,7 @@ class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
class DRAMInterface(MemInterface):
type = 'DRAMInterface'
cxx_header = "mem/mem_interface.hh"
cxx_header = "mem/dram_interface.hh"
cxx_class = 'gem5::memory::DRAMInterface'
# scheduler page policy

2
src/mem/NVMInterface.py
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@@ -44,7 +44,7 @@ from m5.objects.DRAMInterface import AddrMap
# are modeled without getting into too much detail of the media itself.
class NVMInterface(MemInterface):
type = 'NVMInterface'
cxx_header = "mem/mem_interface.hh"
cxx_header = "mem/nvm_interface.hh"
cxx_class = 'gem5::memory::NVMInterface'
# NVM DIMM could have write buffer to offload writes

2
src/mem/SConscript
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@@ -75,6 +75,8 @@ Source('external_master.cc')
Source('external_slave.cc')
Source('mem_ctrl.cc')
Source('mem_interface.cc')
Source('dram_interface.cc')
Source('nvm_interface.cc')
Source('noncoherent_xbar.cc')
Source('packet.cc')
Source('port.cc')

2013
src/mem/dram_interface.cc Normal file
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File diff suppressed because it is too large Load Diff

792
src/mem/dram_interface.hh Normal file
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@@ -0,0 +1,792 @@
/*
* Copyright (c) 2012-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2013 Amin Farmahini-Farahani
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file
* DRAMInterface declaration
*/
#ifndef __DRAM_INTERFACE_HH__
#define __DRAM_INTERFACE_HH__
#include "mem/drampower.hh"
#include "mem/mem_interface.hh"
#include "params/DRAMInterface.hh"
namespace gem5
{
namespace memory
{
/**
* Interface to DRAM devices with media specific parameters,
* statistics, and functions.
* The DRAMInterface includes a class for individual ranks
* and per rank functions.
*/
class DRAMInterface : public MemInterface
{
private:
/**
* Simple structure to hold the values needed to keep track of
* commands for DRAMPower
*/
struct Command
{
Data::MemCommand::cmds type;
uint8_t bank;
Tick timeStamp;
constexpr Command(Data::MemCommand::cmds _type, uint8_t _bank,
Tick time_stamp)
: type(_type), bank(_bank), timeStamp(time_stamp)
{ }
};
/**
* The power state captures the different operational states of
* the DRAM and interacts with the bus read/write state machine,
* and the refresh state machine.
*
* PWR_IDLE : The idle state in which all banks are closed
* From here can transition to: PWR_REF, PWR_ACT,
* PWR_PRE_PDN
*
* PWR_REF : Auto-refresh state. Will transition when refresh is
* complete based on power state prior to PWR_REF
* From here can transition to: PWR_IDLE, PWR_PRE_PDN,
* PWR_SREF
*
* PWR_SREF : Self-refresh state. Entered after refresh if
* previous state was PWR_PRE_PDN
* From here can transition to: PWR_IDLE
*
* PWR_PRE_PDN : Precharge power down state
* From here can transition to: PWR_REF, PWR_IDLE
*
* PWR_ACT : Activate state in which one or more banks are open
* From here can transition to: PWR_IDLE, PWR_ACT_PDN
*
* PWR_ACT_PDN : Activate power down state
* From here can transition to: PWR_ACT
*/
enum PowerState
{
PWR_IDLE = 0,
PWR_REF,
PWR_SREF,
PWR_PRE_PDN,
PWR_ACT,
PWR_ACT_PDN
};
/**
* The refresh state is used to control the progress of the
* refresh scheduling. When normal operation is in progress the
* refresh state is idle. Once tREFI has elasped, a refresh event
* is triggered to start the following STM transitions which are
* used to issue a refresh and return back to normal operation
*
* REF_IDLE : IDLE state used during normal operation
* From here can transition to: REF_DRAIN
*
* REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled
* after self-refresh exit completes
* From here can transition to: REF_DRAIN
*
* REF_DRAIN : Drain state in which on going accesses complete.
* From here can transition to: REF_PD_EXIT
*
* REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed
* Next state dependent on whether banks are open
* From here can transition to: REF_PRE, REF_START
*
* REF_PRE : Close (precharge) all open banks
* From here can transition to: REF_START
*
* REF_START : Issue refresh command and update DRAMPower stats
* From here can transition to: REF_RUN
*
* REF_RUN : Refresh running, waiting for tRFC to expire
* From here can transition to: REF_IDLE, REF_SREF_EXIT
*/
enum RefreshState
{
REF_IDLE = 0,
REF_DRAIN,
REF_PD_EXIT,
REF_SREF_EXIT,
REF_PRE,
REF_START,
REF_RUN
};
class Rank;
struct RankStats : public statistics::Group
{
RankStats(DRAMInterface &dram, Rank &rank);
void regStats() override;
void resetStats() override;
void preDumpStats() override;
Rank &rank;
/*
* Command energies
*/
statistics::Scalar actEnergy;
statistics::Scalar preEnergy;
statistics::Scalar readEnergy;
statistics::Scalar writeEnergy;
statistics::Scalar refreshEnergy;
/*
* Active Background Energy
*/
statistics::Scalar actBackEnergy;
/*
* Precharge Background Energy
*/
statistics::Scalar preBackEnergy;
/*
* Active Power-Down Energy
*/
statistics::Scalar actPowerDownEnergy;
/*
* Precharge Power-Down Energy
*/
statistics::Scalar prePowerDownEnergy;
/*
* self Refresh Energy
*/
statistics::Scalar selfRefreshEnergy;
statistics::Scalar totalEnergy;
statistics::Scalar averagePower;
/**
* Stat to track total DRAM idle time
*
*/
statistics::Scalar totalIdleTime;
/**
* Track time spent in each power state.
*/
statistics::Vector pwrStateTime;
};
/**
* Rank class includes a vector of banks. Refresh and Power state
* machines are defined per rank. Events required to change the
* state of the refresh and power state machine are scheduled per
* rank. This class allows the implementation of rank-wise refresh
* and rank-wise power-down.
*/
class Rank : public EventManager
{
private:
/**
* A reference to the parent DRAMInterface instance
*/
DRAMInterface& dram;
/**
* Since we are taking decisions out of order, we need to keep
* track of what power transition is happening at what time
*/
PowerState pwrStateTrans;
/**
* Previous low-power state, which will be re-entered after refresh.
*/
PowerState pwrStatePostRefresh;
/**
* Track when we transitioned to the current power state
*/
Tick pwrStateTick;
/**
* Keep track of when a refresh is due.
*/
Tick refreshDueAt;
/**
* Function to update Power Stats
*/
void updatePowerStats();
/**
* Schedule a power state transition in the future, and
* potentially override an already scheduled transition.
*
* @param pwr_state Power state to transition to
* @param tick Tick when transition should take place
*/
void schedulePowerEvent(PowerState pwr_state, Tick tick);
public:
/**
* Current power state.
*/
PowerState pwrState;
/**
* current refresh state
*/
RefreshState refreshState;
/**
* rank is in or transitioning to power-down or self-refresh
*/
bool inLowPowerState;
/**
* Current Rank index
*/
uint8_t rank;
/**
* Track number of packets in read queue going to this rank
*/
uint32_t readEntries;
/**
* Track number of packets in write queue going to this rank
*/
uint32_t writeEntries;
/**
* Number of ACT, RD, and WR events currently scheduled
* Incremented when a refresh event is started as well
* Used to determine when a low-power state can be entered
*/
uint8_t outstandingEvents;
/**
* delay low-power exit until this requirement is met
*/
Tick wakeUpAllowedAt;
/**
* One DRAMPower instance per rank
*/
DRAMPower power;
/**
* List of commands issued, to be sent to DRAMPpower at refresh
* and stats dump. Keep commands here since commands to different
* banks are added out of order. Will only pass commands up to
* curTick() to DRAMPower after sorting.
*/
std::vector<Command> cmdList;
/**
* Vector of Banks. Each rank is made of several devices which in
* term are made from several banks.
*/
std::vector<Bank> banks;
/**
* To track number of banks which are currently active for
* this rank.
*/
unsigned int numBanksActive;
/** List to keep track of activate ticks */
std::deque<Tick> actTicks;
/**
* Track when we issued the last read/write burst
*/
Tick lastBurstTick;
Rank(const DRAMInterfaceParams &_p, int _rank,
DRAMInterface& _dram);
const std::string name() const { return csprintf("%d", rank); }
/**
* Kick off accounting for power and refresh states and
* schedule initial refresh.
*
* @param ref_tick Tick for first refresh
*/
void startup(Tick ref_tick);
/**
* Stop the refresh events.
*/
void suspend();
/**
* Check if there is no refresh and no preparation of refresh ongoing
* i.e. the refresh state machine is in idle
*
* @param Return true if the rank is idle from a refresh point of view
*/
bool inRefIdleState() const { return refreshState == REF_IDLE; }
/**
* Check if the current rank has all banks closed and is not
* in a low power state
*
* @param Return true if the rank is idle from a bank
* and power point of view
*/
bool inPwrIdleState() const { return pwrState == PWR_IDLE; }
/**
* Trigger a self-refresh exit if there are entries enqueued
* Exit if there are any read entries regardless of the bus state.
* If we are currently issuing write commands, exit if we have any
* write commands enqueued as well.
* Could expand this in the future to analyze state of entire queue
* if needed.
*
* @return boolean indicating self-refresh exit should be scheduled
*/
bool forceSelfRefreshExit() const;
/**
* Check if the command queue of current rank is idle
*
* @param Return true if the there are no commands in Q.
* Bus direction determines queue checked.
*/
bool isQueueEmpty() const;
/**
* Let the rank check if it was waiting for requests to drain
* to allow it to transition states.
*/
void checkDrainDone();
/**
* Push command out of cmdList queue that are scheduled at
* or before curTick() to DRAMPower library
* All commands before curTick are guaranteed to be complete
* and can safely be flushed.
*/
void flushCmdList();
/**
* Computes stats just prior to dump event
*/
void computeStats();
/**
* Reset stats on a stats event
*/
void resetStats();
/**
* Schedule a transition to power-down (sleep)
*
* @param pwr_state Power state to transition to
* @param tick Absolute tick when transition should take place
*/
void powerDownSleep(PowerState pwr_state, Tick tick);
/**
* schedule and event to wake-up from power-down or self-refresh
* and update bank timing parameters
*
* @param exit_delay Relative tick defining the delay required between
* low-power exit and the next command
*/
void scheduleWakeUpEvent(Tick exit_delay);
void processWriteDoneEvent();
EventFunctionWrapper writeDoneEvent;
void processActivateEvent();
EventFunctionWrapper activateEvent;
void processPrechargeEvent();
EventFunctionWrapper prechargeEvent;
void processRefreshEvent();
EventFunctionWrapper refreshEvent;
void processPowerEvent();
EventFunctionWrapper powerEvent;
void processWakeUpEvent();
EventFunctionWrapper wakeUpEvent;
protected:
RankStats stats;
};
/**
* Function for sorting Command structures based on timeStamp
*
* @param a Memory Command
* @param next Memory Command
* @return true if timeStamp of Command 1 < timeStamp of Command 2
*/
static bool
sortTime(const Command& cmd, const Command& cmd_next)
{
return cmd.timeStamp < cmd_next.timeStamp;
}
/**
* DRAM specific device characteristics
*/
const uint32_t bankGroupsPerRank;
const bool bankGroupArch;
/**
* DRAM specific timing requirements
*/
const Tick tCL;
const Tick tBURST_MIN;
const Tick tBURST_MAX;
const Tick tCCD_L_WR;
const Tick tCCD_L;
const Tick tRCD;
const Tick tRP;
const Tick tRAS;
const Tick tWR;
const Tick tRTP;
const Tick tRFC;
const Tick tREFI;
const Tick tRRD;
const Tick tRRD_L;
const Tick tPPD;
const Tick tAAD;
const Tick tXAW;
const Tick tXP;
const Tick tXS;
const Tick clkResyncDelay;
const bool dataClockSync;
const bool burstInterleave;
const uint8_t twoCycleActivate;
const uint32_t activationLimit;
const Tick wrToRdDlySameBG;
const Tick rdToWrDlySameBG;
enums::PageManage pageMgmt;
/**
* Max column accesses (read and write) per row, before forefully
* closing it.
*/
const uint32_t maxAccessesPerRow;
// timestamp offset
uint64_t timeStampOffset;
// Holds the value of the DRAM rank of burst issued
uint8_t activeRank;
/** Enable or disable DRAM powerdown states. */
bool enableDRAMPowerdown;
/** The time when stats were last reset used to calculate average power */
Tick lastStatsResetTick;
/**
* Keep track of when row activations happen, in order to enforce
* the maximum number of activations in the activation window. The
* method updates the time that the banks become available based
* on the current limits.
*
* @param rank_ref Reference to the rank
* @param bank_ref Reference to the bank
* @param act_tick Time when the activation takes place
* @param row Index of the row
*/
void activateBank(Rank& rank_ref, Bank& bank_ref, Tick act_tick,
uint32_t row);
/**
* Precharge a given bank and also update when the precharge is
* done. This will also deal with any stats related to the
* accesses to the open page.
*
* @param rank_ref The rank to precharge
* @param bank_ref The bank to precharge
* @param pre_tick Time when the precharge takes place
* @param auto_or_preall Is this an auto-precharge or precharge all command
* @param trace Is this an auto precharge then do not add to trace
*/
void prechargeBank(Rank& rank_ref, Bank& bank_ref,
Tick pre_tick, bool auto_or_preall = false,
bool trace = true);
struct DRAMStats : public statistics::Group
{
DRAMStats(DRAMInterface &dram);
void regStats() override;
void resetStats() override;
DRAMInterface &dram;
/** total number of DRAM bursts serviced */
statistics::Scalar readBursts;
statistics::Scalar writeBursts;
/** DRAM per bank stats */
statistics::Vector perBankRdBursts;
statistics::Vector perBankWrBursts;
// Latencies summed over all requests
statistics::Scalar totQLat;
statistics::Scalar totBusLat;
statistics::Scalar totMemAccLat;
// Average latencies per request
statistics::Formula avgQLat;
statistics::Formula avgBusLat;
statistics::Formula avgMemAccLat;
// Row hit count and rate
statistics::Scalar readRowHits;
statistics::Scalar writeRowHits;
statistics::Formula readRowHitRate;
statistics::Formula writeRowHitRate;
statistics::Histogram bytesPerActivate;
// Number of bytes transferred to/from DRAM
statistics::Scalar bytesRead;
statistics::Scalar bytesWritten;
// Average bandwidth
statistics::Formula avgRdBW;
statistics::Formula avgWrBW;
statistics::Formula peakBW;
// bus utilization
statistics::Formula busUtil;
statistics::Formula busUtilRead;
statistics::Formula busUtilWrite;
statistics::Formula pageHitRate;
};
DRAMStats stats;
/**
* Vector of dram ranks
*/
std::vector<Rank*> ranks;
/*
* @return delay between write and read commands
*/
Tick writeToReadDelay() const override { return tBURST + tWTR + tCL; }
/**
* Find which are the earliest banks ready to issue an activate
* for the enqueued requests. Assumes maximum of 32 banks per rank
* Also checks if the bank is already prepped.
*
* @param queue Queued requests to consider
* @param min_col_at time of seamless burst command
* @return One-hot encoded mask of bank indices
* @return boolean indicating burst can issue seamlessly, with no gaps
*/
std::pair<std::vector<uint32_t>, bool>
minBankPrep(const MemPacketQueue& queue, Tick min_col_at) const;
/*
* @return time to send a burst of data without gaps
*/
Tick
burstDelay() const
{
return (burstInterleave ? tBURST_MAX / 2 : tBURST);
}
public:
/**
* Initialize the DRAM interface and verify parameters
*/
void init() override;
/**
* Iterate through dram ranks and instantiate per rank startup routine
*/
void startup() override;
/**
* Setup the rank based on packet received
*
* @param integer value of rank to be setup. used to index ranks vector
* @param are we setting up rank for read or write packet?
*/
void setupRank(const uint8_t rank, const bool is_read) override;
MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
unsigned int size, bool is_read) override;
/**
* Iterate through dram ranks to exit self-refresh in order to drain
*/
void drainRanks() override;
/**
* Return true once refresh is complete for all ranks and there are no
* additional commands enqueued. (only evaluated when draining)
* This will ensure that all banks are closed, power state is IDLE, and
* power stats have been updated
*
* @return true if all ranks have refreshed, with no commands enqueued
*
*/
bool allRanksDrained() const override;
/**
* Iterate through DRAM ranks and suspend them
*/
void suspend() override;
/*
* @return time to offset next command
*/
Tick commandOffset() const override { return (tRP + tRCD); }
/*
* Function to calulate unloaded, closed bank access latency
*/
Tick accessLatency() const override { return (tRP + tRCD + tCL); }
/**
* For FR-FCFS policy, find first DRAM command that can issue
*
* @param queue Queued requests to consider
* @param min_col_at Minimum tick for 'seamless' issue
* @return an iterator to the selected packet, else queue.end()
* @return the tick when the packet selected will issue
*/
std::pair<MemPacketQueue::iterator, Tick>
chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
/**
* Actually do the burst - figure out the latency it
* will take to service the req based on bank state, channel state etc
* and then update those states to account for this request. Based
* on this, update the packet's "readyTime" and move it to the
* response q from where it will eventually go back to the outside
* world.
*
* @param mem_pkt The packet created from the outside world pkt
* @param next_burst_at Minimum bus timing requirement from controller
* @param queue Reference to the read or write queue with the packet
* @return pair, tick when current burst is issued and
* tick when next burst can issue
*/
std::pair<Tick, Tick>
doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
const std::vector<MemPacketQueue>& queue) override;
/**
* Check if a burst operation can be issued to the DRAM
*
* @param Return true if RD/WR can issue
* This requires the DRAM to be in the
* REF IDLE state
*/
bool
burstReady(MemPacket* pkt) const override
{
return ranks[pkt->rank]->inRefIdleState();
}
/**
* This function checks if ranks are actively refreshing and
* therefore busy. The function also checks if ranks are in
* the self-refresh state, in which case, a self-refresh exit
* is initiated.
* The arguments are NVM-specific and will be ignored by DRAM.
* return boolean if all ranks are in refresh and therefore busy
*/
bool isBusy(bool read_queue_empty, bool all_writes_nvm) override;
/**
* Add rank to rank delay to bus timing to all DRAM banks in alli ranks
* when access to an alternate interface is issued
*
* param cmd_at Time of current command used as starting point for
* addition of rank-to-rank delay
*/
void addRankToRankDelay(Tick cmd_at) override;
/**
* Complete response process for DRAM when read burst is complete
* This will update the counters and check if a power down state
* can be entered.
*
* @param rank Specifies rank associated with read burst
*/
void respondEvent(uint8_t rank) override;
/**
* Check the refresh state to determine if refresh needs
* to be kicked back into action after a read response
*
* @param rank Specifies rank associated with read burst
*/
void checkRefreshState(uint8_t rank) override;
/**
* The next three functions are NVM-specific and will be ignored by DRAM.
*/
bool readsWaitingToIssue() const override { return false;}
void chooseRead(MemPacketQueue& queue) override { }
bool writeRespQueueFull() const override { return false;}
DRAMInterface(const DRAMInterfaceParams &_p);
};
} // namespace memory
} // namespace gem5
#endif //__DRAM_INTERFACE_HH__

16
src/mem/mem_ctrl.cc
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@@ -46,7 +46,9 @@
#include "debug/MemCtrl.hh"
#include "debug/NVM.hh"
#include "debug/QOS.hh"
#include "mem/dram_interface.hh"
#include "mem/mem_interface.hh"
#include "mem/nvm_interface.hh"
#include "sim/system.hh"
namespace gem5
@@ -263,11 +265,11 @@ MemCtrl::addToReadQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram)
MemPacket* mem_pkt;
if (is_dram) {
mem_pkt = dram->decodePacket(pkt, addr, size, true, true);
mem_pkt = dram->decodePacket(pkt, addr, size, true);
// increment read entries of the rank
dram->setupRank(mem_pkt->rank, true);
} else {
mem_pkt = nvm->decodePacket(pkt, addr, size, true, false);
mem_pkt = nvm->decodePacket(pkt, addr, size, true);
// Increment count to trigger issue of non-deterministic read
nvm->setupRank(mem_pkt->rank, true);
// Default readyTime to Max; will be reset once read is issued
@@ -342,10 +344,10 @@ MemCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram)
if (!merged) {
MemPacket* mem_pkt;
if (is_dram) {
mem_pkt = dram->decodePacket(pkt, addr, size, false, true);
mem_pkt = dram->decodePacket(pkt, addr, size, false);
dram->setupRank(mem_pkt->rank, false);
} else {
mem_pkt = nvm->decodePacket(pkt, addr, size, false, false);
mem_pkt = nvm->decodePacket(pkt, addr, size, false);
nvm->setupRank(mem_pkt->rank, false);
}
assert(totalWriteQueueSize < writeBufferSize);
@@ -825,8 +827,8 @@ MemCtrl::doBurstAccess(MemPacket* mem_pkt)
// Issue the next burst and update bus state to reflect
// when previous command was issued
std::vector<MemPacketQueue>& queue = selQueue(mem_pkt->isRead());
if (mem_pkt->isDram()) {
std::vector<MemPacketQueue>& queue = selQueue(mem_pkt->isRead());
std::tie(cmd_at, nextBurstAt) =
dram->doBurstAccess(mem_pkt, nextBurstAt, queue);
@@ -836,7 +838,7 @@ MemCtrl::doBurstAccess(MemPacket* mem_pkt)
} else {
std::tie(cmd_at, nextBurstAt) =
nvm->doBurstAccess(mem_pkt, nextBurstAt);
nvm->doBurstAccess(mem_pkt, nextBurstAt, queue);
// Update timing for NVM ranks if NVM is configured on this channel
if (dram)
@@ -923,7 +925,7 @@ MemCtrl::processNextReqEvent()
// check ranks for refresh/wakeup - uses busStateNext, so done after
// turnaround decisions
// Default to busy status and update based on interface specifics
bool dram_busy = dram ? dram->isBusy() : true;
bool dram_busy = dram ? dram->isBusy(false, false) : true;
bool nvm_busy = true;
bool all_writes_nvm = false;
if (nvm) {

1
src/mem/mem_ctrl.hh
View File

@@ -66,6 +66,7 @@ namespace gem5
namespace memory
{
class MemInterface;
class DRAMInterface;
class NVMInterface;

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/*
* Copyright (c) 2010-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2013 Amin Farmahini-Farahani
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/nvm_interface.hh"
#include "base/bitfield.hh"
#include "base/cprintf.hh"
#include "base/trace.hh"
#include "debug/NVM.hh"
#include "sim/system.hh"
namespace gem5
{
namespace memory
{
NVMInterface::NVMInterface(const NVMInterfaceParams &_p)
: MemInterface(_p),
maxPendingWrites(_p.max_pending_writes),
maxPendingReads(_p.max_pending_reads),
twoCycleRdWr(_p.two_cycle_rdwr),
tREAD(_p.tREAD), tWRITE(_p.tWRITE), tSEND(_p.tSEND),
stats(*this),
writeRespondEvent([this]{ processWriteRespondEvent(); }, name()),
readReadyEvent([this]{ processReadReadyEvent(); }, name()),
nextReadAt(0), numPendingReads(0), numReadDataReady(0),
numReadsToIssue(0)
{
DPRINTF(NVM, "Setting up NVM Interface\n");
fatal_if(!isPowerOf2(burstSize), "NVM burst size %d is not allowed, "
"must be a power of two\n", burstSize);
// sanity check the ranks since we rely on bit slicing for the
// address decoding
fatal_if(!isPowerOf2(ranksPerChannel), "NVM rank count of %d is "
"not allowed, must be a power of two\n", ranksPerChannel);
for (int i =0; i < ranksPerChannel; i++) {
// Add NVM ranks to the system
DPRINTF(NVM, "Creating NVM rank %d \n", i);
Rank* rank = new Rank(_p, i, *this);
ranks.push_back(rank);
}
uint64_t capacity = 1ULL << ceilLog2(AbstractMemory::size());
DPRINTF(NVM, "NVM capacity %lld (%lld) bytes\n", capacity,
AbstractMemory::size());
rowsPerBank = capacity / (rowBufferSize *
banksPerRank * ranksPerChannel);
}
NVMInterface::Rank::Rank(const NVMInterfaceParams &_p,
int _rank, NVMInterface& _nvm)
: EventManager(&_nvm), rank(_rank), banks(_p.banks_per_rank)
{
for (int b = 0; b < _p.banks_per_rank; b++) {
banks[b].bank = b;
// No bank groups; simply assign to bank number
banks[b].bankgr = b;
}
}
void
NVMInterface::init()
{
AbstractMemory::init();
}
void NVMInterface::setupRank(const uint8_t rank, const bool is_read)
{
if (is_read) {
// increment count to trigger read and track number of reads in Q
numReadsToIssue++;
} else {
// increment count to track number of writes in Q
numWritesQueued++;
}
}
MemPacket*
NVMInterface::decodePacket(const PacketPtr pkt, Addr pkt_addr,
unsigned size, bool is_read)
{
// decode the address based on the address mapping scheme, with
// Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and
// channel, respectively
uint8_t rank;
uint8_t bank;
// use a 64-bit unsigned during the computations as the row is
// always the top bits, and check before creating the packet
uint64_t row;
// Get packed address, starting at 0
Addr addr = getCtrlAddr(pkt_addr);
// truncate the address to a memory burst, which makes it unique to
// a specific buffer, row, bank, rank and channel
addr = addr / burstSize;
// we have removed the lowest order address bits that denote the
// position within the column
if (addrMapping == enums::RoRaBaChCo || addrMapping == enums::RoRaBaCoCh) {
// the lowest order bits denote the column to ensure that
// sequential cache lines occupy the same row
addr = addr / burstsPerRowBuffer;
// after the channel bits, get the bank bits to interleave
// over the banks
bank = addr % banksPerRank;
addr = addr / banksPerRank;
// after the bank, we get the rank bits which thus interleaves
// over the ranks
rank = addr % ranksPerChannel;
addr = addr / ranksPerChannel;
// lastly, get the row bits, no need to remove them from addr
row = addr % rowsPerBank;
} else if (addrMapping == enums::RoCoRaBaCh) {
// with emerging technologies, could have small page size with
// interleaving granularity greater than row buffer
if (burstsPerStripe > burstsPerRowBuffer) {
// remove column bits which are a subset of burstsPerStripe
addr = addr / burstsPerRowBuffer;
} else {
// remove lower column bits below channel bits
addr = addr / burstsPerStripe;
}
// start with the bank bits, as this provides the maximum
// opportunity for parallelism between requests
bank = addr % banksPerRank;
addr = addr / banksPerRank;
// next get the rank bits
rank = addr % ranksPerChannel;
addr = addr / ranksPerChannel;
// next, the higher-order column bites
if (burstsPerStripe < burstsPerRowBuffer) {
addr = addr / (burstsPerRowBuffer / burstsPerStripe);
}
// lastly, get the row bits, no need to remove them from addr
row = addr % rowsPerBank;
} else
panic("Unknown address mapping policy chosen!");
assert(rank < ranksPerChannel);
assert(bank < banksPerRank);
assert(row < rowsPerBank);
assert(row < Bank::NO_ROW);
DPRINTF(NVM, "Address: %#x Rank %d Bank %d Row %d\n",
pkt_addr, rank, bank, row);
// create the corresponding memory packet with the entry time and
// ready time set to the current tick, the latter will be updated
// later
uint16_t bank_id = banksPerRank * rank + bank;
return new MemPacket(pkt, is_read, false, rank, bank, row, bank_id,
pkt_addr, size);
}
std::pair<MemPacketQueue::iterator, Tick>
NVMInterface::chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const
{
// remember if we found a hit, but one that cannit issue seamlessly
bool found_prepped_pkt = false;
auto selected_pkt_it = queue.end();
Tick selected_col_at = MaxTick;
for (auto i = queue.begin(); i != queue.end() ; ++i) {
MemPacket* pkt = *i;
// select optimal NVM packet in Q
if (!pkt->isDram()) {
const Bank& bank = ranks[pkt->rank]->banks[pkt->bank];
const Tick col_allowed_at = pkt->isRead() ? bank.rdAllowedAt :
bank.wrAllowedAt;
// check if rank is not doing a refresh and thus is available,
// if not, jump to the next packet
if (burstReady(pkt)) {
DPRINTF(NVM, "%s bank %d - Rank %d available\n", __func__,
pkt->bank, pkt->rank);
// no additional rank-to-rank or media delays
if (col_allowed_at <= min_col_at) {
// FCFS within entries that can issue without
// additional delay, such as same rank accesses
// or media delay requirements
selected_pkt_it = i;
selected_col_at = col_allowed_at;
// no need to look through the remaining queue entries
DPRINTF(NVM, "%s Seamless buffer hit\n", __func__);
break;
} else if (!found_prepped_pkt) {
// packet is to prepped region but cannnot issue
// seamlessly; remember this one and continue
selected_pkt_it = i;
selected_col_at = col_allowed_at;
DPRINTF(NVM, "%s Prepped packet found \n", __func__);
found_prepped_pkt = true;
}
} else {
DPRINTF(NVM, "%s bank %d - Rank %d not available\n", __func__,
pkt->bank, pkt->rank);
}
}
}
if (selected_pkt_it == queue.end()) {
DPRINTF(NVM, "%s no available NVM ranks found\n", __func__);
}
return std::make_pair(selected_pkt_it, selected_col_at);
}
void
NVMInterface::chooseRead(MemPacketQueue& queue)
{
Tick cmd_at = std::max(curTick(), nextReadAt);
// This method does the arbitration between non-deterministic read
// requests to NVM. The chosen packet is not removed from the queue
// at this time. Removal from the queue will occur when the data is
// ready and a separate SEND command is issued to retrieve it via the
// chooseNext function in the top-level controller.
assert(!queue.empty());
assert(numReadsToIssue > 0);
numReadsToIssue--;
// For simplicity, issue non-deterministic reads in order (fcfs)
for (auto i = queue.begin(); i != queue.end() ; ++i) {
MemPacket* pkt = *i;
// Find 1st NVM read packet that hasn't issued read command
if (pkt->readyTime == MaxTick && !pkt->isDram() && pkt->isRead()) {
// get the bank
Bank& bank_ref = ranks[pkt->rank]->banks[pkt->bank];
// issueing a read, inc counter and verify we haven't overrun
numPendingReads++;
assert(numPendingReads <= maxPendingReads);
// increment the bytes accessed and the accesses per row
bank_ref.bytesAccessed += burstSize;
// Verify command bandiwth to issue
// Host can issue read immediately uith buffering closer
// to the NVM. The actual execution at the NVM may be delayed
// due to busy resources
if (twoCycleRdWr) {
cmd_at = ctrl->verifyMultiCmd(cmd_at,
maxCommandsPerWindow, tCK);
} else {
cmd_at = ctrl->verifySingleCmd(cmd_at,
maxCommandsPerWindow);
}
// Update delay to next read
// Ensures single read command issued per cycle
nextReadAt = cmd_at + tCK;
// If accessing a new location in this bank, update timing
// and stats
if (bank_ref.openRow != pkt->row) {
// update the open bank, re-using row field
bank_ref.openRow = pkt->row;
// sample the bytes accessed to a buffer in this bank
// here when we are re-buffering the data
stats.bytesPerBank.sample(bank_ref.bytesAccessed);
// start counting anew
bank_ref.bytesAccessed = 0;
// holdoff next command to this bank until the read completes
// and the data has been successfully buffered
// can pipeline accesses to the same bank, sending them
// across the interface B2B, but will incur full access
// delay between data ready responses to different buffers
// in a bank
bank_ref.actAllowedAt = std::max(cmd_at,
bank_ref.actAllowedAt) + tREAD;
}
// update per packet readyTime to holdoff burst read operation
// overloading readyTime, which will be updated again when the
// burst is issued
pkt->readyTime = std::max(cmd_at, bank_ref.actAllowedAt);
DPRINTF(NVM, "Issuing NVM Read to bank %d at tick %d. "
"Data ready at %d\n",
bank_ref.bank, cmd_at, pkt->readyTime);
// Insert into read ready queue. It will be handled after
// the media delay has been met
if (readReadyQueue.empty()) {
assert(!readReadyEvent.scheduled());
schedule(readReadyEvent, pkt->readyTime);
} else if (readReadyEvent.when() > pkt->readyTime) {
// move it sooner in time, to the first read with data
reschedule(readReadyEvent, pkt->readyTime);
} else {
assert(readReadyEvent.scheduled());
}
readReadyQueue.push_back(pkt->readyTime);
// found an NVM read to issue - break out
break;
}
}
}
void
NVMInterface::processReadReadyEvent()
{
// signal that there is read data ready to be transmitted
numReadDataReady++;
DPRINTF(NVM,
"processReadReadyEvent(): Data for an NVM read is ready. "
"numReadDataReady is %d\t numPendingReads is %d\n",
numReadDataReady, numPendingReads);
// Find lowest ready time and verify it is equal to curTick
// also find the next lowest to schedule next event
// Done with this response, erase entry
auto ready_it = readReadyQueue.begin();
Tick next_ready_at = MaxTick;
for (auto i = readReadyQueue.begin(); i != readReadyQueue.end() ; ++i) {
if (*ready_it > *i) {
next_ready_at = *ready_it;
ready_it = i;
} else if ((next_ready_at > *i) && (i != ready_it)) {
next_ready_at = *i;
}
}
// Verify we found the time of this event and remove it
assert(*ready_it == curTick());
readReadyQueue.erase(ready_it);
if (!readReadyQueue.empty()) {
assert(readReadyQueue.front() >= curTick());
assert(!readReadyEvent.scheduled());
schedule(readReadyEvent, next_ready_at);
}
// It is possible that a new command kicks things back into
// action before reaching this point but need to ensure that we
// continue to process new commands as read data becomes ready
// This will also trigger a drain if needed
if (!ctrl->requestEventScheduled()) {
DPRINTF(NVM, "Restart controller scheduler immediately\n");
ctrl->restartScheduler(curTick());
}
}
bool
NVMInterface::burstReady(MemPacket* pkt) const {
bool read_rdy = pkt->isRead() && (ctrl->inReadBusState(true)) &&
(pkt->readyTime <= curTick()) && (numReadDataReady > 0);
bool write_rdy = !pkt->isRead() && !ctrl->inReadBusState(true) &&
!writeRespQueueFull();
return (read_rdy || write_rdy);
}
std::pair<Tick, Tick>
NVMInterface::doBurstAccess(MemPacket* pkt, Tick next_burst_at,
const std::vector<MemPacketQueue>& queue)
{
DPRINTF(NVM, "NVM Timing access to addr %#x, rank/bank/row %d %d %d\n",
pkt->addr, pkt->rank, pkt->bank, pkt->row);
// get the bank
Bank& bank_ref = ranks[pkt->rank]->banks[pkt->bank];
// respect any constraints on the command
const Tick bst_allowed_at = pkt->isRead() ?
bank_ref.rdAllowedAt : bank_ref.wrAllowedAt;
// we need to wait until the bus is available before we can issue
// the command; need minimum of tBURST between commands
Tick cmd_at = std::max(bst_allowed_at, curTick());
// we need to wait until the bus is available before we can issue
// the command; need minimum of tBURST between commands
cmd_at = std::max(cmd_at, next_burst_at);
// Verify there is command bandwidth to issue
// Read burst (send command) is a simple data access and only requires
// one command cycle
// Write command may require multiple cycles to enable larger address space
if (pkt->isRead() || !twoCycleRdWr) {
cmd_at = ctrl->verifySingleCmd(cmd_at, maxCommandsPerWindow);
} else {
cmd_at = ctrl->verifyMultiCmd(cmd_at, maxCommandsPerWindow, tCK);
}
// update the packet ready time to reflect when data will be transferred
// Use the same bus delays defined for NVM
pkt->readyTime = cmd_at + tSEND + tBURST;
Tick dly_to_rd_cmd;
Tick dly_to_wr_cmd;
for (auto n : ranks) {
for (int i = 0; i < banksPerRank; i++) {
// base delay is a function of tBURST and bus turnaround
dly_to_rd_cmd = pkt->isRead() ? tBURST : writeToReadDelay();
dly_to_wr_cmd = pkt->isRead() ? readToWriteDelay() : tBURST;
if (pkt->rank != n->rank) {
// adjust timing for different ranks
// Need to account for rank-to-rank switching with tCS
dly_to_wr_cmd = rankToRankDelay();
dly_to_rd_cmd = rankToRankDelay();
}
n->banks[i].rdAllowedAt = std::max(cmd_at + dly_to_rd_cmd,
n->banks[i].rdAllowedAt);
n->banks[i].wrAllowedAt = std::max(cmd_at + dly_to_wr_cmd,
n->banks[i].wrAllowedAt);
}
}
DPRINTF(NVM, "NVM Access to %#x, ready at %lld.\n",
pkt->addr, pkt->readyTime);
if (pkt->isRead()) {
// completed the read, decrement counters
assert(numPendingReads != 0);
assert(numReadDataReady != 0);
numPendingReads--;
numReadDataReady--;
} else {
// Adjust number of NVM writes in Q
assert(numWritesQueued > 0);
numWritesQueued--;
// increment the bytes accessed and the accesses per row
// only increment for writes as the reads are handled when
// the non-deterministic read is issued, before the data transfer
bank_ref.bytesAccessed += burstSize;
// Commands will be issued serially when accessing the same bank
// Commands can issue in parallel to different banks
if ((bank_ref.bank == pkt->bank) &&
(bank_ref.openRow != pkt->row)) {
// update the open buffer, re-using row field
bank_ref.openRow = pkt->row;
// sample the bytes accessed to a buffer in this bank
// here when we are re-buffering the data
stats.bytesPerBank.sample(bank_ref.bytesAccessed);
// start counting anew
bank_ref.bytesAccessed = 0;
}
// Determine when write will actually complete, assuming it is
// scheduled to push to NVM immediately
// update actAllowedAt to serialize next command completion that
// accesses this bank; must wait until this write completes
// Data accesses to the same buffer in this bank
// can issue immediately after actAllowedAt expires, without
// waiting additional delay of tWRITE. Can revisit this
// assumption/simplification in the future.
bank_ref.actAllowedAt = std::max(pkt->readyTime,
bank_ref.actAllowedAt) + tWRITE;
// Need to track number of outstanding writes to
// ensure 'buffer' on media controller does not overflow
assert(!writeRespQueueFull());
// Insert into write done queue. It will be handled after
// the media delay has been met
if (writeRespQueueEmpty()) {
assert(!writeRespondEvent.scheduled());
schedule(writeRespondEvent, bank_ref.actAllowedAt);
} else {
assert(writeRespondEvent.scheduled());
}
writeRespQueue.push_back(bank_ref.actAllowedAt);
writeRespQueue.sort();
if (writeRespondEvent.when() > bank_ref.actAllowedAt) {
DPRINTF(NVM, "Rescheduled respond event from %lld to %11d\n",
writeRespondEvent.when(), bank_ref.actAllowedAt);
DPRINTF(NVM, "Front of response queue is %11d\n",
writeRespQueue.front());
reschedule(writeRespondEvent, bank_ref.actAllowedAt);
}
}
// Update the stats
if (pkt->isRead()) {
stats.readBursts++;
stats.bytesRead += burstSize;
stats.perBankRdBursts[pkt->bankId]++;
stats.pendingReads.sample(numPendingReads);
// Update latency stats
stats.totMemAccLat += pkt->readyTime - pkt->entryTime;
stats.totBusLat += tBURST;
stats.totQLat += cmd_at - pkt->entryTime;
} else {
stats.writeBursts++;
stats.bytesWritten += burstSize;
stats.perBankWrBursts[pkt->bankId]++;
}
return std::make_pair(cmd_at, cmd_at + tBURST);
}
void
NVMInterface::processWriteRespondEvent()
{
DPRINTF(NVM,
"processWriteRespondEvent(): A NVM write reached its readyTime. "
"%d remaining pending NVM writes\n", writeRespQueue.size());
// Update stat to track histogram of pending writes
stats.pendingWrites.sample(writeRespQueue.size());
// Done with this response, pop entry
writeRespQueue.pop_front();
if (!writeRespQueue.empty()) {
assert(writeRespQueue.front() >= curTick());
assert(!writeRespondEvent.scheduled());
schedule(writeRespondEvent, writeRespQueue.front());
}
// It is possible that a new command kicks things back into
// action before reaching this point but need to ensure that we
// continue to process new commands as writes complete at the media and
// credits become available. This will also trigger a drain if needed
if (!ctrl->requestEventScheduled()) {
DPRINTF(NVM, "Restart controller scheduler immediately\n");
ctrl->restartScheduler(curTick());
}
}
void
NVMInterface::addRankToRankDelay(Tick cmd_at)
{
// update timing for NVM ranks due to bursts issued
// to ranks for other media interfaces
for (auto n : ranks) {
for (int i = 0; i < banksPerRank; i++) {
// different rank by default
// Need to only account for rank-to-rank switching
n->banks[i].rdAllowedAt = std::max(cmd_at + rankToRankDelay(),
n->banks[i].rdAllowedAt);
n->banks[i].wrAllowedAt = std::max(cmd_at + rankToRankDelay(),
n->banks[i].wrAllowedAt);
}
}
}
bool
NVMInterface::isBusy(bool read_queue_empty, bool all_writes_nvm)
{
DPRINTF(NVM,"isBusy: numReadDataReady = %d\n", numReadDataReady);
// Determine NVM is busy and cannot issue a burst
// A read burst cannot issue when data is not ready from the NVM
// Also check that we have reads queued to ensure we can change
// bus direction to service potential write commands.
// A write cannot issue once we've reached MAX pending writes
// Only assert busy for the write case when there are also
// no reads in Q and the write queue only contains NVM commands
// This allows the bus state to switch and service reads
return (ctrl->inReadBusState(true) ?
(numReadDataReady == 0) && !read_queue_empty :
writeRespQueueFull() && read_queue_empty &&
all_writes_nvm);
}
NVMInterface::NVMStats::NVMStats(NVMInterface &_nvm)
: statistics::Group(&_nvm),
nvm(_nvm),
ADD_STAT(readBursts, statistics::units::Count::get(),
"Number of NVM read bursts"),
ADD_STAT(writeBursts, statistics::units::Count::get(),
"Number of NVM write bursts"),
ADD_STAT(perBankRdBursts, statistics::units::Count::get(),
"Per bank write bursts"),
ADD_STAT(perBankWrBursts, statistics::units::Count::get(),
"Per bank write bursts"),
ADD_STAT(totQLat, statistics::units::Tick::get(),
"Total ticks spent queuing"),
ADD_STAT(totBusLat, statistics::units::Tick::get(),
"Total ticks spent in databus transfers"),
ADD_STAT(totMemAccLat, statistics::units::Tick::get(),
"Total ticks spent from burst creation until serviced "
"by the NVM"),
ADD_STAT(avgQLat, statistics::units::Rate<
statistics::units::Tick, statistics::units::Count>::get(),
"Average queueing delay per NVM burst"),
ADD_STAT(avgBusLat, statistics::units::Rate<
statistics::units::Tick, statistics::units::Count>::get(),
"Average bus latency per NVM burst"),
ADD_STAT(avgMemAccLat, statistics::units::Rate<
statistics::units::Tick, statistics::units::Count>::get(),
"Average memory access latency per NVM burst"),
ADD_STAT(avgRdBW, statistics::units::Rate<
statistics::units::Byte, statistics::units::Second>::get(),
"Average DRAM read bandwidth in MiBytes/s"),
ADD_STAT(avgWrBW, statistics::units::Rate<
statistics::units::Byte, statistics::units::Second>::get(),
"Average DRAM write bandwidth in MiBytes/s"),
ADD_STAT(peakBW, statistics::units::Rate<
statistics::units::Byte, statistics::units::Second>::get(),
"Theoretical peak bandwidth in MiByte/s"),
ADD_STAT(busUtil, statistics::units::Ratio::get(),
"NVM Data bus utilization in percentage"),
ADD_STAT(busUtilRead, statistics::units::Ratio::get(),
"NVM Data bus read utilization in percentage"),
ADD_STAT(busUtilWrite, statistics::units::Ratio::get(),
"NVM Data bus write utilization in percentage"),
ADD_STAT(pendingReads, statistics::units::Count::get(),
"Reads issued to NVM for which data has not been transferred"),
ADD_STAT(pendingWrites, statistics::units::Count::get(),
"Number of outstanding writes to NVM"),
ADD_STAT(bytesPerBank, statistics::units::Byte::get(),
"Bytes read within a bank before loading new bank")
{
}
void
NVMInterface::NVMStats::regStats()
{
using namespace statistics;
perBankRdBursts.init(nvm.ranksPerChannel == 0 ? 1 :
nvm.banksPerRank * nvm.ranksPerChannel);
perBankWrBursts.init(nvm.ranksPerChannel == 0 ? 1 :
nvm.banksPerRank * nvm.ranksPerChannel);
avgQLat.precision(2);
avgBusLat.precision(2);
avgMemAccLat.precision(2);
avgRdBW.precision(2);
avgWrBW.precision(2);
peakBW.precision(2);
busUtil.precision(2);
busUtilRead.precision(2);
busUtilWrite.precision(2);
pendingReads
.init(nvm.maxPendingReads)
.flags(nozero);
pendingWrites
.init(nvm.maxPendingWrites)
.flags(nozero);
bytesPerBank
.init(nvm.rowBufferSize)
.flags(nozero);
avgQLat = totQLat / readBursts;
avgBusLat = totBusLat / readBursts;
avgMemAccLat = totMemAccLat / readBursts;
avgRdBW = (bytesRead / 1000000) / simSeconds;
avgWrBW = (bytesWritten / 1000000) / simSeconds;
peakBW = (sim_clock::Frequency / nvm.tBURST) *
nvm.burstSize / 1000000;
busUtil = (avgRdBW + avgWrBW) / peakBW * 100;
busUtilRead = avgRdBW / peakBW * 100;
busUtilWrite = avgWrBW / peakBW * 100;
}
} // namespace memory
} // namespace gem5

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/*
* Copyright (c) 2012-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2013 Amin Farmahini-Farahani
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file
* NVMInterface declaration
*/
#ifndef __NVM_INTERFACE_HH__
#define __NVM_INTERFACE_HH__
#include "mem/mem_interface.hh"
#include "params/NVMInterface.hh"
namespace gem5
{
namespace memory
{
/**
* Interface to NVM devices with media specific parameters,
* statistics, and functions.
* The NVMInterface includes a class for individual ranks
* and per rank functions.
*/
class NVMInterface : public MemInterface
{
private:
/**
* NVM rank class simply includes a vector of banks.
*/
class Rank : public EventManager
{
public:
/**
* Current Rank index
*/
uint8_t rank;
/**
* Vector of NVM banks. Each rank is made of several banks
* that can be accessed in parallel.
*/
std::vector<Bank> banks;
Rank(const NVMInterfaceParams &_p, int _rank,
NVMInterface& _nvm);
};
/**
* NVM specific device and channel characteristics
*/
const uint32_t maxPendingWrites;
const uint32_t maxPendingReads;
const bool twoCycleRdWr;
/**
* NVM specific timing requirements
*/
const Tick tREAD;
const Tick tWRITE;
const Tick tSEND;
struct NVMStats : public statistics::Group
{
NVMStats(NVMInterface &nvm);
void regStats() override;
NVMInterface &nvm;
/** NVM stats */
statistics::Scalar readBursts;
statistics::Scalar writeBursts;
statistics::Vector perBankRdBursts;
statistics::Vector perBankWrBursts;
// Latencies summed over all requests
statistics::Scalar totQLat;
statistics::Scalar totBusLat;
statistics::Scalar totMemAccLat;
// Average latencies per request
statistics::Formula avgQLat;
statistics::Formula avgBusLat;
statistics::Formula avgMemAccLat;
statistics::Scalar bytesRead;
statistics::Scalar bytesWritten;
// Average bandwidth
statistics::Formula avgRdBW;
statistics::Formula avgWrBW;
statistics::Formula peakBW;
statistics::Formula busUtil;
statistics::Formula busUtilRead;
statistics::Formula busUtilWrite;
/** NVM stats */
statistics::Histogram pendingReads;
statistics::Histogram pendingWrites;
statistics::Histogram bytesPerBank;
};
NVMStats stats;
void processWriteRespondEvent();
EventFunctionWrapper writeRespondEvent;
void processReadReadyEvent();
EventFunctionWrapper readReadyEvent;
/**
* Vector of nvm ranks
*/
std::vector<Rank*> ranks;
/**
* Holding queue for non-deterministic write commands, which
* maintains writes that have been issued but have not completed
* Stored seperately mostly to keep the code clean and help with
* events scheduling.
* This mimics a buffer on the media controller and therefore is
* not added to the main write queue for sizing
*/
std::list<Tick> writeRespQueue;
std::deque<Tick> readReadyQueue;
/**
* Check if the write response queue is empty
*
* @param Return true if empty
*/
bool writeRespQueueEmpty() const { return writeRespQueue.empty(); }
/**
* Till when must we wait before issuing next read command?
*/
Tick nextReadAt;
// keep track of reads that have issued for which data is either
// not yet ready or has not yet been transferred to the ctrl
uint16_t numPendingReads;
uint16_t numReadDataReady;
public:
// keep track of the number of reads that have yet to be issued
uint16_t numReadsToIssue;
/**
* Initialize the NVM interface and verify parameters
*/
void init() override;
/**
* Setup the rank based on packet received
*
* @param integer value of rank to be setup. used to index ranks vector
* @param are we setting up rank for read or write packet?
*/
void setupRank(const uint8_t rank, const bool is_read) override;
MemPacket* decodePacket(const PacketPtr pkt, Addr pkt_addr,
unsigned int size, bool is_read) override;
/**
* Check drain state of NVM interface
*
* @return true if write response queue is empty
*
*/
bool allRanksDrained() const override { return writeRespQueueEmpty(); }
/*
* @return time to offset next command
*/
Tick commandOffset() const override { return tBURST; }
/**
* Check if a burst operation can be issued to the NVM
*
* @param Return true if RD/WR can issue
* for reads, also verfy that ready count
* has been updated to a non-zero value to
* account for race conditions between events
*/
bool burstReady(MemPacket* pkt) const override;
/**
* This function checks if ranks are busy.
* This state is true when either:
* 1) There is no command with read data ready to transmit or
* 2) The NVM inteface has reached the maximum number of outstanding
* writes commands.
* @param read_queue_empty There are no read queued
* @param all_writes_nvm All writes in queue are for NVM interface
* @return true of NVM is busy
*
*/
bool isBusy(bool read_queue_empty, bool all_writes_nvm) override;
/**
* For FR-FCFS policy, find first NVM command that can issue
* default to first command to prepped region
*
* @param queue Queued requests to consider
* @param min_col_at Minimum tick for 'seamless' issue
* @return an iterator to the selected packet, else queue.end()
* @return the tick when the packet selected will issue
*/
std::pair<MemPacketQueue::iterator, Tick>
chooseNextFRFCFS(MemPacketQueue& queue, Tick min_col_at) const override;
/**
* Add rank to rank delay to bus timing to all NVM banks in alli ranks
* when access to an alternate interface is issued
*
* param cmd_at Time of current command used as starting point for
* addition of rank-to-rank delay
*/
void addRankToRankDelay(Tick cmd_at) override;
/**
* Following two functions are not required for nvm interface
*/
void respondEvent(uint8_t rank) override { };
void checkRefreshState(uint8_t rank) override { };
/**
* Select read command to issue asynchronously
*/
void chooseRead(MemPacketQueue& queue) override;
/*
* Function to calulate unloaded access latency
*/
Tick accessLatency() const override { return (tREAD + tSEND); }
/**
* Check if the write response queue has reached defined threshold
*
* @param Return true if full
*/
bool
writeRespQueueFull() const override
{
return writeRespQueue.size() == maxPendingWrites;
}
bool
readsWaitingToIssue() const override
{
return ((numReadsToIssue != 0) &&
(numPendingReads < maxPendingReads));
}
/**
* Actually do the burst and update stats.
*
* @param pkt The packet created from the outside world pkt
* @param next_burst_at Minimum bus timing requirement from controller
* @return pair, tick when current burst is issued and
* tick when next burst can issue
*/
std::pair<Tick, Tick>
doBurstAccess(MemPacket* pkt, Tick next_burst_at,
const std::vector<MemPacketQueue>& queue) override;
/**
* The next three functions are DRAM-specific and will be ignored by NVM.
*/
void drainRanks() override { }
void suspend() override { }
void startup() override { }
NVMInterface(const NVMInterfaceParams &_p);
};
} // namespace memory
} // namespace gem5
#endif //__NVM_INTERFACE_HH__