Commit Graph

17 Commits

Author SHA1 Message Date
Gabe Black
a19bb5f5ab arch,cpu: Turn (read|set)*Reg into inline helpers.
Eliminate readFloatRegFlat and setFloatRegFlat for the Fast Model
ThreadContext since ARM doesn't use those register types, and those
methods are no longer required by the ThreadContext interface.

Change-Id: Ic149c64e2fbf1d313066fefe480c435eef6d66e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49113
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-14 21:48:37 +00:00
Gabe Black
3ca13734ac cpu: Implement getReg and setReg for O3.
Change-Id: I3f0bf1e75a5191be98c79fede5aad854a920e9c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49109
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-02-10 23:56:37 +00:00
Gabe Black
528d184ac7 misc: Linearlize VecElem indexing.
These registers used to be accessed with a two dimensional index, with
one dimension specifying the register, and the second index specifying
the element within that register. This change linearizes that index down
to one dimension, where the elements of each register are laid out one
after the other in sequence.

Change-Id: I41110f57b505679a327108369db61c826d24922e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49148
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-01-21 23:05:47 +00:00
Gabe Black
3e766837b0 arch,cpu: Stop using TheISA::Decoder in most places.
The only places that still use that indirection are where the decoder
itself is instantiated with "new".

Also, add an "as" method which makes casting to an ISA specific decoder
type easier and less error prone.

Change-Id: Ib4a9cce7f96da2a9a8fe19113628694904893b17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52079
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
8279191cd9 misc,cpu: Make ThreadContext work with PCStateBase-s.
Change-Id: I92f1d79c697bb45f610604c9e84b24ea93d58776
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52058
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-30 23:30:06 +00:00
Gabe Black
4fe56ff720 arch-arm,cpu: Replace rename modes with split reg/elem register files.
This simplifies the O3 CPU, and removes special cases around how vector
registers are handled. Now ARM is responsible for maintaining its
different register personalities internally.

Also, this re-establishes the invariant that registers are indexed as
complete, opaque entities with no internal structure, at least as far as
the CPU is concerned.

To make sure the KVM CPU sees the correct state, we need to sync over
the vector registers if we're in 32 bit mode when moving state to or
from gem5's ThreadContext.

Change-Id: I36416d609310ae0bc50c18809f5d9e19bfbb4d37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49147
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-28 06:00:07 +00:00
Gabe Black
9b1abd4d83 cpu: Use RegVal for VecElems instead of TheISA::VecElem.
If VecElem is a basic type, which is a reasonable assumption, it can be
contained in a RegVal. We still need to use the TheISA::VecElem type to
extract it from an actual vector, but then it can be passed around as a
RegVal.

Change-Id: I4dc470e7cc369499ce3686dd291eb3d93ca0819a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49124
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-11 04:48:02 +00:00
Gabe Black
a6e023906e fastmodel,cpu: Eliminate the unused getVirtProxy.
Change-Id: I84683a3297143102a74ac6dfe744cd5804b83fe4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45908
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-23 08:59:36 +00:00
Daniel R. Carvalho
974a47dfb9 misc: Adopt the gem5 namespace
Apply the gem5 namespace to the codebase.

Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.

A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.

std out should not be included in the gem5 namespace, so
they weren't.

ProtoMessage has not been included in the gem5 namespace,
since I'm not familiar with how proto works.

Regarding the SystemC files, although they belong to gem5,
they actually perform integration between gem5 and SystemC;
therefore, it deserved its own separate namespace.

Files that are automatically generated have been included
in the gem5 namespace.

The .isa files currently are limited to a single namespace.
This limitation should be later removed to make it easier
to accomodate a better API.

Regarding the files in util, gem5:: was prepended where
suitable. Notice that this patch was tested as much as
possible given that most of these were already not
previously compiling.

Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-01 19:08:24 +00:00
Gabe Black
d9bda9c2be cpu,fastmodel: Get rid of unused (read|set)FuncExeInst.
These zombie methods were plumbed around and looked like they might do
something, but nothing actually uses them.

Change-Id: I1e85669202e2ecb10370e6c6eb8364eb47085cf3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45919
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-05-28 18:51:55 +00:00
Gabe Black
9909ea8a40 cpu: Create an O3 namespace and simplify O3 names.
DefaultFoo => Foo
O3Foo => Foo
FullO3CPU => CPU

DerivO3CPU => O3CPU (python)

DerivO3 => o3::CPU

Change-Id: I04551214442633c79c33e9d86b067ff3ec0d1a8d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42120
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-25 19:29:14 +00:00
Gabe Black
157f9757c2 cpu: De-templatize the O3ThreadContext.
Change-Id: I1559760949031bd63bd3a48e62c37448c1f6f5b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42115
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
2021-05-21 01:19:37 +00:00
Gabe Black
6687265fe2 cpu: Delete authors lists from the cpu directory.
Change-Id: Icfba8e23b5f6820a6ddefe1a50abbe5f8825b7b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25444
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-02-17 21:51:23 +00:00
BKP
1246617fb2 style: change C/C++ source permissions to noexec
Several files in the repository were tracked with execute permissions
even though the files are just normal C/C++ files (and the one .isa).

Change-Id: I976b096acab4a1fc74c5699ef1f9b222c1e635c2
Reviewed-on: https://gem5-review.googlesource.com/7241
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-10 16:49:23 +00:00
Brandon Potter
7a8dda49a4 style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
Nathan Binkert
39a055645f includes: sort all includes 2011-04-15 10:44:06 -07:00
Gabe Black
b66eb3b8d1 O3: Generaize the O3 IMPL class so it isn't split out by ISA.
--HG--
rename : src/cpu/o3/sparc/cpu_builder.cc => src/cpu/o3/cpu_builder.cc
rename : src/cpu/o3/sparc/dyn_inst.cc => src/cpu/o3/dyn_inst.cc
rename : src/cpu/o3/sparc/impl.hh => src/cpu/o3/impl.hh
rename : src/cpu/o3/sparc/thread_context.cc => src/cpu/o3/thread_context.cc
2008-10-09 00:10:02 -07:00