Commit Graph

22305 Commits

Author SHA1 Message Date
Harshil Patel
63d25922a2 tests: Update pyunit tests references to include 24.1 (#1843) 2024-12-07 00:02:57 -08:00
Vishnu Ramadas
8877516e5b mem-ruby: Fix GPU_VIPER-TCP.sm atomic transitions in TCC WB mode
The transition that happens when TCC acknowledges TCP of an atomic
operation completion does not move the cacheline state from A to I. This
commit fixes the transition and moves the state to I
2024-12-06 23:17:46 -08:00
Vishnu Ramadas
6aa9db28f1 mem-ruby: Fix segfault in pa_performAtomics in GPU_VIPER-TCC.sm
When the cache is performing an atomics and receives data, it performs.
pa_performAtomic. This action peeks into the coreRequest queue to check
the messaage type. This queue, however, is already dequeued in the
transition that precedes the one that contains pa_performAtomic. When
pa_performAtomic is called, the simulation crashes. This commit fixes
the crash by using the TBE entry information instead of peeking when TBE
entry exists, and peeking when it doesn't
2024-12-06 23:17:10 -08:00
Jason Lowe-Power
93b58fbf64 misc: Add GPU info to release notes (#1844)
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Co-authored-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Co-authored-by: Matt Sinclair <mattdsinclair.wisc@gmail.com>
2024-12-06 21:59:24 -08:00
Bobby R. Bruce
ae60062a9e mem-ruby,misc: Fix RNG range (#1842)
This upper range must be `UINT_MAX - 1`. This was previously fixed but
reverted back. Without this the RNG crashes.
2024-12-06 21:58:52 -08:00
Bobby R. Bruce
26ba6dad80 scons: Remove warn as error for v24.1 2024-12-06 19:45:58 -08:00
Erin Le
4559bafaa6 arch-riscv: Remove warning message in senvcfg setMiscReg
Previously, a warning would be printed when the WPRI bits
in the senvcfg register were written to. The other registers
do not print warnings for this, so the warning is being
removed.
2024-12-06 19:38:39 -08:00
Erin Le
e6b931213f arch-riscv: Implement behavior for senvcfg register
This commit adds behavior for writes to the senvcfg register.
It also implements the CBIE, CBCFE, and CBZE bitfields of
senvcfg.
2024-12-06 19:38:24 -08:00
Erin Le
3b62f1f8e4 arch-riscv: Add senvcfg CSR
This commit adds the senvcfg CSR, which fixes the 6.11.3 kernel
crash documented in issue 1674. I have not added a bitfield and
its implementation in isa.cc only uses setMiscRegNoEffect, so
this implementation is likely missing some critical components.
2024-12-06 19:38:14 -08:00
Erin (Jianghua) Le
8f37677c9b misc: v24.1 release notes update (#1840) 2024-12-06 16:13:43 -08:00
Clement Dieperink
2b645ed38c arch-riscv: fix tlb stats in timming mode (#1832)
The previous #484 issue reported a bug where the TLB stats on RISC-V
were incremented twice on misses by calling the `lookup` function twice
with hidden argument set to `false`. The fix is only applied on atomic
mode as the `translation` argument of `doTranslate` will not be
`nullptr` in timing mode.

In that case, if the TLB lookup miss, the `doTranslate` function will
start the walker and then return without doing anything more. Then
later, when the pagetable walker found the corresponding PTE, it will
insert it and call `translateWithTLB`. This function then call `lookup`
again which will hit in any case (and crash if not due to the following
assert), but the hit count is incremented here too. 

This commit fix by setting the `hidden` argument of `lookup` to true.
2024-12-06 11:27:52 -08:00
Bobby R. Bruce
3711bf8a7a base,arch-arm: Add GEM5_NO_OPTIMIZE; use in ARM's vfp.hh (#1834)
GCC and CLANG have different annotations for declaring code should not
be optimized. Adding GEM5_NO_OPTIMZE provides gem5 developers a MACRO
that works in both cases.

This change replaces the GCC pragmas in vfp.hh with GEM5_NO_OPTIMIZE
as this solution didn't work with clang.
2024-12-04 21:36:18 -08:00
Jason Lowe-Power
5672d63ae4 mem-ruby: Fix functional access in MI_example (#1838)
In MI_example, when in MI state the block "Maybe_Stale" as in this
controller may have the most up to date value or it could be in the
network. For MII it is guaranteed that this controller has the most up
to date value because it received a PUTX_NACK.

This fixes one of the daily test failures.
2024-12-04 21:35:46 -08:00
Harshil Patel
a8db1fc683 scons: get protocol info from slicc instead of file parsing 2024-12-04 21:35:14 -08:00
Harshil Patel
02a5ddaeac mem-ruby, scons: Add ProtocolInfo.hh files in build targets
- In the new MultiRuby system, the generated ProtocolInfo header files were not being correctly added to the build targets in SCons.

- As a result, when building gem5 with the --duplicate-sources option, these files were mistakenly deleted by SCons.
This happened because SCons treated them as source files instead of generated build targets.

- This commit ensures that the ProtocolInfo header files are explicitly included in the build targets, preventing their unintended removal and fixing the build issue.
2024-12-04 21:34:54 -08:00
Bobby R. Bruce
dee42f1867 arch-riscv: Remove CPU_SET use for non-linux host (#1835)
For non-Linux systems, we use cpu_set_cpu. CPU_SET is a macro that is
not available for non-Linux systems.

Fixes #1720
2024-12-04 15:48:49 -08:00
2channelkrt
f799d91309 ruby-chi: fix wrong ruby-CHI base class name (#1817)
fix ruby-CHI base class name so it actually runs

previously was combined with PR #1797
2024-12-04 15:47:44 -08:00
Giacomo Travaglini
8a9f61c546 misc: Add CHI section to the RELEASE-NOTES.md (#1833)
Change-Id: I2f01dd9c7a45c5f6baf57e4aad0f171417a6efb1

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2024-12-03 00:47:08 -08:00
Bobby R. Bruce
59ca5600ec misc: Update version info for v24.1 2024-12-02 11:10:28 -08:00
Giacomo Travaglini
c64a807f94 misc: Add ArmISA section to the RELEASE-NOTES.md file (#1822) 2024-12-02 09:38:02 -08:00
Junshi Wang
0a22e63467 arch-arm: Fix bug in VQRSHL.
If shiftAmt is 0, bits raise assert, causing core dump.

Change-Id: Ic4285f51a866ffc017645655e98674ca69a15a40
2024-12-02 08:46:57 -08:00
Erin (Jianghua) Le
1e5021c2e3 tests: modify gem5/learning-gem5 ref file to fix failure (#1795)
The test `ruby_test_test-ALL-x86_64-opt-MatchStdout` is currently
failing because the reference file doesn't match the actual output. This
PR changes the reference file to match.
2024-12-02 08:46:10 -08:00
Nicholas Mosier
25523e73a4 arch-x86, sim-se: move mmap end downward in case of large stacks (#1810)
Fix #1809. Shift the mmap end to a lower address in case the process has
a large max stack size, to avoid overlapping the stack with the mmap
memory range.

Change-Id: Idae343dbbe851a7510463ff141c03f1847e36328
2024-12-02 08:44:54 -08:00
Giacomo Travaglini
1b16697029 mem-ruby: Fix conflict between 117 and 1084
This is fixing the conflict between the multi-ruby [1] and the CHI-TLM
[2] PRs

[1]: https://github.com/gem5/gem5/pull/117
[2]: https://github.com/gem5/gem5/pull/1084

Change-Id: Ie9c6381c361ac344e22984d8a53ed03c387b0b43
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2024-12-02 08:43:58 -08:00
Harshil Patel
e51bc00dc7 misc: revert riscvmatched-fs.py due to a bug
- link to issue https://github.com/gem5/gem5/issues/1554

Change-Id: Ic9cf6e5166eeee2226b6022e6f7c971d4e7caaeb
2024-12-02 08:41:58 -08:00
Erin (Jianghua) Le
e221a70355 Add ExitEvent import to arm-ubuntu-run.py 2024-12-02 08:41:58 -08:00
Harshil Patel
630173a845 misc: update fs examples to use ubuntu 24.04 boot workloads
Change-Id: I7e16f69eff3a7ff0ab16c18e6d35e846d07ac829
2024-12-02 08:41:55 -08:00
Roger Chang
40ccb8b171 arch-riscv: Use getValidAddr to get zero-extend address in RV32 mode
Previous PR #1758 implements the generic getValidAddr to get pure
vaddr without any tags or sign-extend bits.

In RISC-V implementation, the getValidAddr will zero-extend
address in RV32 mode and use it to do TLB translation. Use
getValidAddr to get zero-extend vaddr can reduce zero-extend
repetition

Change-Id: I2273ce48bccb873790103ba0fcdb0b48de9ced4c
2024-12-02 08:33:15 -08:00
studyztp
3a2cfb2dee cpu: fix looppoint anaylsis param python string spacing
Change-Id: I98fe434f1066f12b975425e49baca6e6a6087dab
2024-12-02 08:33:14 -08:00
studyztp
0f0a6a7851 cpu: fix pc count pair helper function return type
Change the helper function's return type from int to uint64_t

Change-Id: I34b6b563a6333bbf8516a16d2ad4b76b7c16bfe4
2024-12-02 08:33:14 -08:00
studyztp
4ce0f20436 cpu: make PcCountPair use 64 bit unsigned int for count
In PcCountPair param, change the type for "count" from 32 bit int to
64 bit unsigned int.

Change-Id: I2dc1bb2692914f06eaaae9bd5bbfb061bcbbfb8b
2024-12-02 08:33:14 -08:00
studyztp
6a9db637ae cpu: add function to get inst map of each basic block
Change-Id: I147d8c90cdfc7bf795d1c6a6daf96e11fa1c0858
2024-12-02 08:33:14 -08:00
studyztp
7ffa3646bd cpu: fix the incorrect debug message
Change-Id: I062e359e8c9205a9a993a33865434922c1f540b8
2024-12-02 08:33:14 -08:00
studyztp
1410c29147 cpu: modified after review feedback
src/cpu/simple/probes/LooppointAnalysis.py:
- remove default values for bb_valid_addr_range and
marker_valid_addr_range
- add more comments to explain parameter behaviors
- add citation to the LoopPoint paper

src/cpu/simple/probes/looppoint_analysis.cc:
- fix the incorrect styles
- remove updateBackwardBranch() function call
- match the style of checking if listeners vector is empty
- change the way of stopListening() to remove the listeners through the
manager instead of through the ProbeListener object's destructor.

src/cpu/simple/probes/looppoint_analysis.hh:
- removed backwardBranchPC and use the backwardBranchCounter to replace
its functionaility. Therefore, also removed updateBackwardBranch
function.

Change-Id: Id2430e2f04e61f72d5c4f1aad5cfd4d24a0fbc45
2024-12-02 08:33:14 -08:00
studyztp
89717eca3c cpu: add more debug flags
Change-Id: I4edd8f383294f76d3e76895d3a631cba21a45f90
2024-12-02 08:33:14 -08:00
studyztp
753d9971d2 cpu: add more comments to looppoint_analysis.cc
Change-Id: I027db66ffed0cd5957bae2a9a36286ca1c73c313
2024-12-02 08:33:14 -08:00
studyztp
a1072357c1 cpu: fix a issue
Change-Id: Iab621e294c84c7f5c704882b0c681f950ad08f9c
2024-12-02 08:33:13 -08:00
studyztp
abc8a4a483 cpu: fix a wrong file path
Change-Id: I93343f4053c7a6d1bd4b6972a1e7c3dbc073c979
2024-12-02 08:33:13 -08:00
studyztp
cd29b199ce cpu: add the python class
Add the python classes for the LooppointAnalysis and the
LooppointAnalysis Manager.

Change-Id: I0a882bc1a9ef03b7b482e871a7160e7c33f9ac08
2024-12-02 08:33:13 -08:00
studyztp
e10fff4876 cpu: add looppoint_analysis.cc content
Add LooppointAnalysis and LooppointAnalysisManager function definitions

Change-Id: I1c05072ebf1b744ee102a82f8de2b93bab4a056f
2024-12-02 08:33:13 -08:00
studyztp
fff6c895fe cpu: add comments and improve naming in looppoint_analysis.hh
Add comments to most variables and functions.
Change the naming of some variables and functions to improve the
clearness.

Change-Id: Idb557ec84698b4344ed4683f5de87b1a3c2fd66d
2024-12-02 08:33:13 -08:00
studyztp
3c7c7b8b54 cpu: add looppoint_analysis.hh content and licenses
In looppoint_analysis.hh, added LooppointAnalysis and
LooppointAnalysisManager classes.
Added all functions and variables for the classes.
Comments needed.

Change-Id: Ia7425b672ef092a68c99b702136850bfa1fcf0a2
2024-12-02 08:33:13 -08:00
studyztp
157d89e255 cpu: add basic files for LoopPoint analysis
Because the LoopPoint analysis will be done with ATOMIC CPU, so all
files related to the LoopPoint analysis object will be under
/src/cpu/simple/probes.

Change-Id: Icbdb0742b712a23dc8f6a19f4c1c827a1f5bf288
2024-12-02 08:33:13 -08:00
Matthew Poremba
9fe8c7cd74 stdlib: Updates to VIPER board after all protocols PR 2024-12-02 08:33:13 -08:00
Jason Lowe-Power
6cf5a46f68 stdlib: Update names for GPU children
This change updates the names for the GPU children in a better way than
overriding the parent. Now it looks something like

```text
board.gpus.shader.CUs00
board.gpus.gpu_caches.ruby_gpu.controllers02
board.gpus.memory.mem_ctrl0
```

Note that it is "gpus" with an "s" because the board accepts more than 1
GPU, optionally.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2024-12-02 08:33:12 -08:00
Jason Lowe-Power
c75c267e34 stdlib: Remove debug prints
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2024-12-02 08:33:12 -08:00
Jason Lowe-Power
e93f498aac stdlib: Add get_devices to abstract board
This function returns the GPUs (for now, possibly other devices in the
future). It needs to be in the abstract board so the GPU-specific cache
hierarchies can be used with non-GPU boards.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2024-12-02 08:33:12 -08:00
Jason Lowe-Power
bec9ae77e6 stdlib: Override the readfile contents in GPU board
This prepends loading the GPU drivers to anything passed in via the
readfile_contents. Note that if the user sets a specific readfile via a
file they will be responsible for loading the driver

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2024-12-02 08:33:12 -08:00
Mahyar Samani
2fca39cec7 dev-amdgpu: Separating gpu_memory from gpu_cache.
This change separates the instantiation of gpu memory from
instantiatiing the gpu cache. Prior to this change, the gpu
cache instantiated the memories for the gpu by receiving number
of channels as a parameter. With this change, the gpu memory
should be constructed outside the gpu, without being added as a
child to any other object, and passed to the constructor of
the gpu.
2024-12-02 08:33:12 -08:00
Mahyar Samani
1948155fb2 stdlib: AbstractMemorySystem.get_mem_interfaces.
This change adds a new method to AbstractMemorySystem to allow
getting its objects of the class MemInterface. This is useful
when certain other classes require a list of MemInterface objects
to create physical memory. In addition, ChanneledMemory and
HighBandwidthMemory implement this function.
2024-12-02 08:33:12 -08:00