derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

stdlib: Updates to VIPER board after all protocols PR

Browse Source
This commit is contained in:
Matthew Poremba
2024-10-31 07:18:49 -07:00
committed by Bobby R. Bruce
parent 6cf5a46f68
commit 9fe8c7cd74
10 changed files with 44 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/python/gem5/components/cachehierarchies/ruby/caches/viper/corepair_cache.py
View File

@@ -30,7 +30,7 @@
import math
from m5.objects import (
CorePair_Controller,
GPU_VIPER_CorePair_Controller,
MessageBuffer,
RubyCache,
TreePLRURP,
@@ -39,7 +39,7 @@ from m5.objects import (
from gem5.components.processors.abstract_core import AbstractCore
class CorePairCache(CorePair_Controller):
class CorePairCache(GPU_VIPER_CorePair_Controller):
def __init__(
self,
l1i_size: str,

13
src/python/gem5/components/cachehierarchies/ruby/caches/viper/directory.py
View File

@@ -29,17 +29,17 @@
from m5.objects import (
GPU_VIPER_Directory_Controller,
MessageBuffer,
RubyDirectoryMemory,
)
from ......utils.override import overrides
from ..abstract_directory import AbstractDirectory
class ViperDirectory(AbstractDirectory):
class ViperDirectory(GPU_VIPER_Directory_Controller):
def __init__(self, network, cache_line_size, mem_range, port):
super().__init__(network, cache_line_size)
super().__init__()
self._cache_line_size = cache_line_size
self.addr_ranges = [mem_range]
self.directory = RubyDirectoryMemory(
block_size=cache_line_size,
@@ -58,7 +58,8 @@ class ViperDirectory(AbstractDirectory):
self.useL3OnWT = False
self.L2isWB = False
@overrides(AbstractDirectory)
self.connectQueues(network)
def connectQueues(self, network):
self.requestFromDMA = MessageBuffer(ordered=True)
self.requestFromDMA.in_port = network.out_port

23
src/python/gem5/components/cachehierarchies/ruby/caches/viper/dma_controller.py
View File

@@ -28,19 +28,21 @@
# POSSIBILITY OF SUCH DAMAGE.
from m5.objects import MessageBuffer
from ......utils.override import overrides
from ..abstract_dma_controller import AbstractDMAController
from m5.objects import (
GPU_VIPER_DMA_Controller,
MessageBuffer,
)
# There is a controller for GPU and GPU to keep the "version" numbers
# incrementing seperately
class ViperCPUDMAController(AbstractDMAController):
class ViperCPUDMAController(GPU_VIPER_DMA_Controller):
def __init__(self, network, cache_line_size):
super().__init__(network, cache_line_size)
super().__init__()
self._cache_line_size = cache_line_size
self.connectQueues(network)
@overrides(AbstractDMAController)
def connectQueues(self, network):
# A buffer size of 0 means it is an infinite queue. The VIPER
# DMA controller has not been thoroughly tested with finite buffers.
@@ -52,11 +54,12 @@ class ViperCPUDMAController(AbstractDMAController):
self.requestToDir.out_port = network.in_port
class ViperGPUDMAController(AbstractDMAController):
class ViperGPUDMAController(GPU_VIPER_DMA_Controller):
def __init__(self, network, cache_line_size):
super().__init__(network, cache_line_size)
super().__init__()
self.connectQueues(network)
@overrides(AbstractDMAController)
def connectQueues(self, network):
# A buffer size of 0 means it is an infinite queue. The VIPER
# DMA controller has not been thoroughly tested with finite buffers.

4
src/python/gem5/components/cachehierarchies/ruby/caches/viper/sqc.py
View File

@@ -28,14 +28,14 @@
# POSSIBILITY OF SUCH DAMAGE.
from m5.objects import (
GPU_VIPER_SQC_Controller,
MessageBuffer,
RubyCache,
SQC_Controller,
TreePLRURP,
)
class SQCCache(SQC_Controller):
class SQCCache(GPU_VIPER_SQC_Controller):
def __init__(
self,
sqc_size: str,

4
src/python/gem5/components/cachehierarchies/ruby/caches/viper/tcc.py
View File

@@ -28,14 +28,14 @@
# POSSIBILITY OF SUCH DAMAGE.
from m5.objects import (
GPU_VIPER_TCC_Controller,
MessageBuffer,
RubyCache,
TCC_Controller,
TreePLRURP,
)
class TCCCache(TCC_Controller):
class TCCCache(GPU_VIPER_TCC_Controller):
def __init__(
self,
tcc_size: str,

4
src/python/gem5/components/cachehierarchies/ruby/caches/viper/tcp.py
View File

@@ -28,14 +28,14 @@
# POSSIBILITY OF SUCH DAMAGE.
from m5.objects import (
GPU_VIPER_TCP_Controller,
MessageBuffer,
RubyCache,
TCP_Controller,
TreePLRURP,
)
class TCPCache(TCP_Controller):
class TCPCache(GPU_VIPER_TCP_Controller):
def __init__(
self,
tcp_size: str,

4
src/python/gem5/prebuilt/viper/board.py
View File

@@ -72,6 +72,10 @@ class ViperBoard(X86Board):
self.gpus = gpus
@overrides(AbstractCacheHierarchy)
def get_coherence_protocol(self):
return CoherenceProtocol.GPU_VIPER
@overrides(AbstractBoard)
def get_devices(self):
return self.gpus

2
src/python/gem5/prebuilt/viper/cpu_cache_hierarchy.py
View File

@@ -219,6 +219,7 @@ class ViperCPUCacheHierarchy(AbstractRubyCacheHierarchy):
)
ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port)
ctrl.version = len(self._dma_controllers)
ctrl.ruby_system = self.ruby_system
ctrl.dma_sequencer.ruby_system = self.ruby_system
@@ -239,6 +240,7 @@ class ViperCPUCacheHierarchy(AbstractRubyCacheHierarchy):
version=len(self._dma_controllers), in_ports=port
)
ctrl.version = len(self._dma_controllers)
ctrl.ruby_system = self.ruby_system
ctrl.dma_sequencer.ruby_system = self.ruby_system

1
src/python/gem5/prebuilt/viper/gpu_cache_hierarchy.py
View File

@@ -277,6 +277,7 @@ class ViperGPUCacheHierarchy(AbstractRubyCacheHierarchy):
)
ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port)
ctrl.version = len(self._dma_controllers)
ctrl.ruby_system = self.ruby_gpu
ctrl.dma_sequencer.ruby_system = self.ruby_gpu

11
src/python/gem5/prebuilt/viper/viper_network.py
View File

@@ -91,8 +91,15 @@ class SimpleDoubleCrossbar(SimpleNetwork):
self.ruby_system = ruby_system
def connect(self, controllers):
l2_xbar_types = ("TCP_Controller", "SQC_Controller", "TCC_Controller")
soc_xbar_types = ("DMA_Controller", "Directory_Controller")
l2_xbar_types = (
"GPU_VIPER_TCP_Controller",
"GPU_VIPER_SQC_Controller",
"GPU_VIPER_TCC_Controller",
)
soc_xbar_types = (
"GPU_VIPER_DMA_Controller",
"GPU_VIPER_Directory_Controller",
)
# Create one router per controller plus a crossbar for L2 controllers
# and a crossbar for SoC controllers.