Commit Graph

21283 Commits

Author SHA1 Message Date
Richard Cooper
f21df19fd7 misc: Add function to extract the Linux Kernel Version
This function, `extract_kernel_version`, attempts to find the Kernel
version by searching the `uts_namespace` struct at the exported symbol
`init_uts_ns`. This structure contains the Kernel version as a string,
and is referenced by `procfs` to return the Kernel version in a
running system.

Different versions of the Kernel use different layouts for this
structure, and the top level structure is marked as
`__randomize_layout`, so the exact layout in memory cannot be relied
on. Because of this, `extract_kernel_version` takes the approach of
searching the memory holding the structure for printable strings, and
parsing the version from those strings.

Change-Id: If8b2e81a041af891fd6e56a87346a341df3c9728
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2023-12-01 22:00:36 +00:00
Richard Cooper
7ecff99c25 base: Add a size field to the Symbol object
Add a size field to the Symbol objects in the Symbol Table. This
allows client code to read the data associated with a symbol in cases
where the data type/size is not known beforehand (e.g. if an object's
size might be different between different versions of a
workload/kernel).

Access is mediated via the `sizeOrDefault()` method, which requires
client code to specify a fallback size. Since correct size data may
not be available (for example in legacy checkpoints), this forces the
client code to consider the 'missing size data' case.

Change-Id: If1a47463790b25beadf94f84382e3b7392ab2f04
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2023-12-01 22:00:35 +00:00
Richard Cooper
2fbbdad618 base: Add encapsulation to the loader::Symbol class
This commit converts `gem5::loader::Symbol` to a full class with
private members, enforcing encapsulation. Until now client code has
been able to (and does) access members directly.

This change will enable class invariants to be enforced via accessor
methods.

Change-Id: Ia0b5b080d4f656637a211808e13dce1ddca74541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2023-12-01 22:00:26 +00:00
Bobby R. Bruce
88601d3ac5 stdlib: Add ShadowResource
The purpose of a `ShadowResource` is a resource which only contains the
ID and Version information, not any additional information about the
resource thus avoiding the `obtain_resource` call.

When attributes of the `ShadowResource` are accessed which can only be
obtained via `obtain_resource` the `ShowResource` calls the function and
returns what is required.

This is useful for `Suite` resources which contain several workloads
and resources which may not all be needed when the `Suite` object is
first instantiated.

Change-Id: Icc56261b2c4d74e4079ee66486ddae677bb35cfa
2023-12-01 13:38:08 -08:00
anoop
fc0a043950 mem-ruby: Unused L3CacheCntrl freed (#598)
Seems like the MOESI_AMD_Base-L3Cache.sm file is unused in the VIPER
protocol. It's confusing to have it in the GPU_VIPER.slicc file.
2023-12-01 13:01:19 -08:00
Ivana Mitrovic
d96b6cdae7 misc, stdlib: Update documentation to adhere to RST formatting. (#631)
This PR updates files in `src/python` to adhere to reStructuredText
formatting.
2023-12-01 11:43:49 -08:00
Matt Sinclair
0a2f9d4b18 mem-ruby: update CacheMemory RubyCache debug prints
Update the RubyCache debug flag prints in CacheMemory to be more
descriptive and make clearer what is happening in a given function.
This makes it easier to determine what is happening when looking at the
RubyCache debug flags prints.

Change-Id: Ieee172b6df0d100f4b1e8fe4bba872fc9cf65854
2023-12-01 12:31:52 -06:00
Hoa Nguyen
be3163a072 stdlib: Integrate BootloaderKernelWorkload
Change-Id: Ifeaa98059d5667c3335eaccd57a5295f44f88e43
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-12-01 07:28:30 +00:00
Hoa Nguyen
bbe5216d88 arch-riscv: Rename BootloaderKernelWorkload parameters
The gem5 standard library hardcoded some parameters of the workload.
E.g., the kernel filename must be `object_file`.

Change-Id: I5eeb7359be399138693eaba0738eaf524c59408f
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-12-01 07:28:30 +00:00
Bobby R. Bruce
bfd25f5352 util-docker: Enforce cmake version >=3.24 for DRAMSys (#627)
DRAMSys requires cmake 3.24 or greater. By default neither Ubuntu 22.04
or 20.04 delevery this by APT.

In both cases wget is required. In 20.04 OpenSSL is required.

Then ext/dramsys README file has been updated to state this requirement.
2023-11-30 21:23:53 -08:00
Bobby R. Bruce
743b2aada6 stdlib: Move resource download to get_local_path
This change decouple's the downloading of a resource from it's data.
With this change the `obtain_resource` function returns the
`AbstractResource` implementation which contains the data. The resource
itself (e.g., the actual disk image, binary, file, etc.) is only
downloaded to the host system, if not already present, upon the
`get_local_path` call.

`get_local_path` is the function used by gem5 to ultimately load the
resource into a simulation, therefore this change ensures we only
download resources when they are loaded into a simulation.

This change is not ideal and comes with the following caveats:

1. The `downloader` function is created in `obtain_workload` and passed
to the `AbstractResource` implementation for later use. This function
comes with the following requirements:
    * The function will download the resource to `local_path`.
    * The function will not re-download the resources if already present
as this function is called _everytime_ `get_local_path` is called.
2. The directories needed to store `local_path` are created in
`obtain_workload` regardless. Ergo even if the resource is not used and
`get_local_path` is never called these directories are still created.

Change-Id: I3f0e9a0099cba946630d719c3d17b7da0bccf74a
2023-11-30 15:27:44 -08:00
Jason Lowe-Power
62a2b6eed2 ext: Update readme for DRAMSys
Specify the cmake version

Change-Id: I8bbdb128667df37724c38caef5572d8fb1641ef5
2023-11-30 15:09:28 -08:00
Jason Lowe-Power
b3e7af9d79 Support for classic prefetchers in Ruby (#502)
This patch adds supports for using the "classic" prefetchers with ruby
cache controllers.

This pull request includes a few commits making the changes in this
order:
- Refactor decouples the classic cache and prefetchers interfaces
- Extras probes for later integration with ruby
- General ruby-side support
- Adds support for the CHI protocol

Commit [mem-ruby: support prefetcher in CHI
protocol](2bdb65653b)
may be used as example on how to add support for other protocols.

JIRA issues that may be related to this pull request:
    https://gem5.atlassian.net/browse/GEM5-457
    https://gem5.atlassian.net/browse/GEM5-1112
2023-11-30 10:24:29 -08:00
Yu-Cheng Chang
a16fd8a592 scons: Limit adding fastmodel files and libpath (#629)
The change will only add include and library path if the fastmodel is
required to build. The change will benefit for most of gem5 build.

Change-Id: I98c20bd1470b7227940036199e02bc001e307eac
2023-11-30 07:36:26 -08:00
Jason Lowe-Power
9afe9932bc sim,python: Restore sigint handler in python (#531)
Currently, if you try to use ctrl-c while python code is running nothing
happens. This is not ideal. This change enables users to use ctrl-c
while python is running (e.g., when a large disk image is downloading).
To do this, we moved the `initSignals` function in gem5 from `main` to
the simulate loop. Thus, every time the simulate loop starts (i.e., is
called from python) gem5 will install its signal handlers. Also, when
the control is returned to python, we put python's default SIGINT
handler back.

Change-Id: I14490e48d931eb316e8c641217bf8d8ddaa340ed
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2023-11-30 07:27:52 -08:00
Andreas Sandberg
dcdebec0f6 misc,python: Add isort hook to pre-commit (#431) 2023-11-30 09:54:12 +00:00
Bobby R. Bruce
d11c40dcac misc: Run pre-commit run --all-files
This ensures `isort` is applied to all files in the repo.

Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
2023-11-29 22:06:41 -08:00
Bobby R. Bruce
7d67109ca2 python,misc: Add isort to pre-commit
Change-Id: I391a8948f0817bd5c6a9fe8a4c3e4fed07a98c49
2023-11-29 22:06:05 -08:00
Bobby R. Bruce
f256064b4a util-docker: Enforce cmake version >=3.24 for DRAMSys
DRAMSys requires cmake 3.24 or greater. By default neither Ubuntu 22.04
or 20.04 delevery this by APT.

In both cases wget is required. In 20.04 OpenSSL is required.

Change-Id: I51a7f8a8a46e8cf1908a120adb9289aa3907ccda
2023-11-29 21:49:11 -08:00
Bobby R. Bruce
b99af93183 misc: Merge .github directory from develop to stable (#626) 2023-11-29 19:04:13 -08:00
Bobby R. Bruce
403bf38a0e tests: switch lulesh/hacc to use vega_x86 (#620) 2023-11-29 18:55:53 -08:00
Harshil Patel
b59a398312 tests: change HACC tests to VEGA_X86
Change-Id: I846229db1ab1480d79471c717b714698c3132df9
2023-11-29 16:02:30 -08:00
Harshil Patel
392086b43d stdlib, resources: removed deprecated if statement in obtain_resource for workload resources (#611)
- The resources field in workload now changed to a dict of id and
version from a string with just the id.
There was an if statement added to support both versions in develop.
Removing the if statement so that 23.1 supports the new changes only.

Change-Id: Id8dc3f932f53a156e4fb609a215db7d85bd81a44
2023-11-29 14:27:23 -08:00
Bobby R. Bruce
fcbcd1ce72 arch-x86: Fixes page fault for CLFLUSH on write-protected pages (#592)
Converts CLFLUSHOPT/WB/FLUSH operations from Write to Read operations
during address translation so that they don't trigger a page fault when
done on write-protected pages.

Solves #226
2023-11-29 14:25:21 -08:00
Hoa Nguyen
1d1cba297b scons: Add an option to reduce memory usage of ld (#601)
Linking the gem5 binary consists of linking numerous object files. By
default, ld optimizes for speed over for memory consumption [1]. This
leads to the huge memory consumption of gem5 at the linking stage.

This patch adds an option to add the `--no-keep-memory` flag to ld.
According to the documentation [1], this flag optimizes the memory usage
of ld.

[1]
https://ftp.gnu.org/old-gnu/Manuals/ld-2.9.1/html_chapter/ld_2.html#IDX133

Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-11-29 14:24:48 -08:00
Yu-Cheng Chang
57ba3fccb7 scons: Move CPPPATH systemc_home to "src/systemc" folder (#617)
Files under src/systemc require the include path of systemc_home

Change-Id: Ibcbac2762259a0b997ac444b2c63a218c27af9ee
2023-11-29 13:56:23 -08:00
Bobby R. Bruce
a2e7bd4698 arch-riscv: Support combination of privilege modes configuration (#522)
The user can select privilege modes witch is included in the system, not
always enable the user and supervisor privilege modes.
2023-11-29 10:12:57 -08:00
Adrià Armejach
b0cefac9b2 arch-riscv: Fix narrow datatypes in RVV isa files (#606)
Some variables hava narrow datatypes that overflow on large VLEN values.
For example, the maximum number of microops for LMUL=8 SEW=8 and
VLEN=64K is 2^16.

Change-Id: I5cce759f040884e09ce83bee7e54a62c4b42c5aa

Co-authored-by: Adrià Armejach <adria.armejach@bsc.es>
2023-11-29 10:11:06 -08:00
Adrià Armejach
eb13b32314 cpu-o3: Fix discarded requests str-ld forwarding (#614)
With the use of large RVV vectors (i.e., 8K or 16K bits) and a limited
number of cacheLoadPorts, some loads take multiple cycles to execute.
This triggered certain conditions when store-to-load forwarding happens
in the middle of the execution of a load that already has outstanding
packets.

First, after store-to-load forwarding the request is marked as discarded
and the load is immediately writtenback, which triggers a writebackDone
that tries to delete the request, triggering an assert as it still has
outstanding packets. This patch avoid deleting the request leaving it
self owned, it will be deleted when the last packet arrives in
packetReplied.

Second, this patch avoid checking snoops on discarded requests by
checking if the request exists.

Change-Id: Icea0add0327929d3a6af7e6dd0af9945cb0d0970

Co-authored-by: Adrià Armejach <adria.armejach@bsc.es>
2023-11-29 08:45:03 -08:00
Harshil Patel
089b82b2e9 arch-riscv: fix tlb bug (#610)
- one tlb miss was getting counted twice by the lookup function.

Change-Id: I5fee08bd6e936896704e7dbbd242720b8d23b547
2023-11-29 08:39:02 -08:00
Harshil Patel
23cadf0886 tests: switch lulesh to use vega_x86
Change-Id: Ifbf0fdfd7d8c2bbaad0b6094090acecd1cb8055c
2023-11-29 07:41:51 -08:00
Tiago Mück
0f8c60bce5 mem-ruby: add missing state for CHI Prefetch event
RUSC state is missing for the Prefetch event.

Change-Id: If440ac0052100dba295708471a75a24cd234c011
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:50 -06:00
Tiago Mück
91cf58871e mem-ruby: support prefetcher in CHI protocol
Use RubyPrefetcherProxy to support prefetchers in the
CHI cache controller

L1I/L1D/L2 prefechers can now be added by specifying a non-null
prefetcher type when configuring a CHI_RNF.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Additional authors:
    Tuan Ta <tuan.ta2@arm.com>

Change-Id: I41dc637969acaab058b22a8c9c3931fa137eeace
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:50 -06:00
Tiago Mück
94d5cc17a2 mem-ruby,mem-cache: ruby supports classic pfs
This patch adds RubyPrefetcherProxy, which provides means to inject
requests generated by the "classic" prefetchers into a SLICC prefetch
queue. It defines defines notifyPf* functions to be used by protocols
to notify a prefetcher. It also includes the probes required to
interface with the classic implementation.
AbstractController defines the accessor needed to snoop the caches.

A followup patch will add support for RubyPrefetcherProxy in the
CHI protocol.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Additional authors:
    Tuan Ta <tuan.ta2@arm.com>

Change-Id: Ie908150b510f951cdd6fd0fd9c95d9760ff70fb0
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:50 -06:00
Tiago Mück
3a7192d682 mem-cache: change hasBeenPrefetched
hasBeenPrefetched can now take a requestor id and returns true only if
the block was prefetched by a prefetcher with the same id. This may be
necessary to properly train multiple prefetchers attached to the same
cache. If returns true if the block was prefetched by any prefetcher
when the id is not provided.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Change-Id: I205e000fd5ff100e5a5d24d88bca7c6a46689ab2
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:49 -06:00
Tiago Mück
a63ff3c442 mem-cache: add prefetcher listener for evictions
Listener to data update probe notifies prefetcher of evictions.
Prefetchers need to implement notifyEvict to make use of this
information.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Change-Id: I052cfdeba1e40ede077554ada104522f6a0cb2c7
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:49 -06:00
Tiago Mück
d8a04f902e mem-cache: add prefetch info to update probe
CacheDataUpdateProbeArg has additional info to tell listeners if the
block was prefetched and evicted without being used, as well as which
object prefetched the block.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Change-Id: Id8ac9099ddbce6e94ee775655da23de5df25cf0f
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:49 -06:00
Tiago Mück
becba00d95 mem-cache,configs: remove extra prefetch_* params
Remove the prefetch_on_access and prefetch_on_pf_hit from BaseCache.
BasePrefetch no longer expects this params to exist in the parent.

Configurations that set these parameter using the cache object were
fixed.

Change-Id: I9ab6a545eaf930ee41ebda74e2b6b8bad0ca35a7
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:49 -06:00
Tiago Mück
af2ee0db30 mem-cache: decoupled prefetchers from cache
This patches decouples the prefetchers from the cache implementation
as the first step to allow using the classic prefetchers with ruby
caches. The prefetchers that need do cache lookups can do so using
the accessor object provided when the probes are notified. This may
also facilitate connecting the same prefetcher to multiple caches.

Related JIRA:
https://gem5.atlassian.net/browse/GEM5-457
https://gem5.atlassian.net/browse/GEM5-1112

Change-Id: I4fee1a3613ae009fabf45d7b747e4582cad315ef
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
2023-11-28 18:30:49 -06:00
Jason Lowe-Power
3fe5e58f28 arch-x86: Fix misc registers in mov instructions (#593)
MOV instructions 8C and 8E can be prefixed with a REX prefix to extend
the source/destination register.
However, the R bit in REX will be applied to the segment register.  
The decoder file checks for valid segment registers, checking the
MODRM_REG only, however, later this will be extended with the REX_R when
adding the register to the sources/destinations of the instruction.
This will trigger an assert.

Additionally, MOV instructions of various miscelaneous registers are
also not check for being valid when taking into account the REX_R bit.

This patch checks that the REX_R is not set, otherwise, UD2 will be
generated.
2023-11-28 11:14:53 -08:00
Andreas Sandberg
0c30353c59 cpu: Require BTB hit to detect branches. (#493)
In a high performance CPU there is no other way than a BTB hit
to know about a branch instruction and its type. For low-end CPU's
pre-decoding might sit in from of the BPU to provide this information.
Currently, the BPU models only low-end behavior and updates the
RAS and the indirect branch prediction even without a BTB hit.
This patch adds three things to model the correct behavior for high-end
CPUs.
1. A check before the RAS and indirect predictor wheather there was
a BTB hit or not. Only for BTB hits the BPU will consolidate RAS, and
indirect predictor.
2. Since, this check requires a BTB hit for indirect branches they must
also be installed into the BTB. For returns this was already done.
3. Finally, the BTB update previously happened at squash (decode
or commit). Since this can be out-of-order that means branches from
the false path can get installed without ever been retired.
2023-11-28 09:39:14 +00:00
Roger Chang
9a0c671cce arch-riscv: Handle the exception following the privilege mode set
Change-Id: I4867941ec286fe485e01db848b8c7357488f6cf4
2023-11-28 09:26:27 +08:00
Roger Chang
d56801c240 arch-riscv: Add misa rvs check for memory translation
The memory translation require supervisor mode implement. If the
supervisor mode is not implemented, the satp CSR is not exists and
should not do address translation

Change-Id: Ie6c8a1a130d0aab0647b35e0f731f6b930834176
2023-11-28 09:26:27 +08:00
Roger Chang
6fd4feb797 arch-riscv: fatal_if the process run without SU modes
Change-Id: Ifce7eec6cea10881964c29d206a92f3d10271de6
2023-11-28 09:26:27 +08:00
Roger Chang
9e738a65ea arch-riscv: Add isaExts field for CSR registers
Change-Id: Idd94af57f3a721d455ea7fb9d335fab7b16a0f7e
2023-11-28 09:26:27 +08:00
Roger Chang
0e4f82a119 arch-riscv: define the CSR masks for each privilege modes
Change-Id: I9936d9bc816921a827b94550847d4898b3aa3292
2023-11-28 09:26:27 +08:00
Roger Chang
f745e8cf89 arch-riscv: Initial the privilege modes configuration
1. Declare the new enum type PrivilegeModes
2. Disallow setting the MISA register RVU and RVS.

Change-Id: I932d714bc70c9720a706353c557a5be76c950f81
2023-11-28 09:26:27 +08:00
aditya
c00209a0c0 Merge branch 'x86-clflush-fault-fix' of github.com:AKKamath/gem5 into x86-clflush-fault-fix
Change-Id: Ia9a694b0f7ef99331430cdb796c252ce8bb51f3b
2023-11-28 00:42:27 +00:00
Aditya K Kamath
9a0566e295 arch-x86: Fixes page fault for CLFLUSH on write-protected pages
Converts CLFLUSHOPT/WB/FLUSH operations from Write to Read operations
during address translation so that they don't trigger a page fault
when done on write-protected pages.

Change-Id: I20e89cc0cb2b288b36ba1f0ba39a2e1bf0f728af
2023-11-28 00:42:17 +00:00
Bobby R. Bruce
3bf0b1d22a misc: Merge develop .github dir to stable (#608) 2023-11-27 14:32:51 -08:00