Commit Graph

18073 Commits

Author SHA1 Message Date
Gabe Black
2887a996e1 fastmodel: Don't try to "staticify" system libraries.
We want to insist that the fast model libraries are the static versions
so they don't have to be found on non-system paths at run time, but we
don't need or want to do the same for system libraries which are from
standard paths on the host system.

Split the set of libraries fast model adds to the build into ones that
come from fast model itself, and ones it needs which should be
provided by the system. The ones from fast model itself should still
go through staticify, but the system libraries should be passed to the
compiler generically so it can pick which version it wants.

Change-Id: I222c94f8117143b86377150e686a4af669a994fe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51627
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-14 11:39:52 +00:00
Giacomo Travaglini
133997d515 arch-arm: Add chdir implementation to the Syscall Table
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I584d9269b0445347dd65071f7fc5569c8ac24b89
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51549
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-14 08:52:39 +00:00
Giacomo Travaglini
54d48c0244 sim-se, kern: Add flags parameter to unlinkat
The unlinkat syscall expects a "third" flags parameter [1].

It is using it to implement a sort of rmdirat (in case the parameter
includes the AT_REMOVEDIR flag)

[1]: https://man7.org/linux/man-pages/man2/unlink.2.html

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I38dd9268ae4de0f289abe779c4da03e969248065
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51548
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-14 08:52:39 +00:00
Giacomo Travaglini
65ef21a308 sim-se: Define rmdirImpl helper
This will be used by the following commit when properly reimplementing
unlinkat syscall

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: If207bed196ad467decaa1cfee70a538e6dfe8d1d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51547
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-14 08:52:39 +00:00
Gabe Black
bad6fa679d scons: Don't explicitly list include dependencies for the cxx config.
SCons will scan c/c++ files for include dependencies itself, there's no
need to list them explicitly.

Change-Id: I295c22e52e38c53ab7705193f2fe2c98227ea70d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49403
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
2021-10-14 01:59:23 +00:00
Matt Sinclair
16c49af22e tests: convert all nightly GPU tests from GUID to GID
As part of the docker commands for the nightly GPU regression tests,
earlier commits inadvertently used GUID instead of GID, where GUID does
not exist.  This causes some failures when run in Jenkins.  This patch
fixes this issue.

Change-Id: I429c079ae3df9fd97a956f23a2fc9baeed3f7377
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51567
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-14 01:20:31 +00:00
Gabe Black
7290bf52f3 mem: Replace SatCounter with SatCounter8 in the SHiP replacement policy.
Change-Id: Ibbc8e78df7119cdff62ad08b5c68f4237ca25cfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51530
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 23:13:57 +00:00
Bobby R. Bruce
66db68359a tests: Fix the nightly GPU tests
The nightly tests failed:
https://www.mail-archive.com/gem5-dev@gem5.org/msg40828.html

This failure was due to new GPU tests assuming tests were executed from
the `tests` directory. They are actually executed from the gem5 root.
This patch fixes the error.

Change-Id: Ie5f86ef4eb13134a2a3d0291422f65c9ee355a92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51607
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 22:37:53 +00:00
Mahyar Samani
eb25cbd9d7 cpu: Adding GUPSGen ClockedObject.
This patch adds the code base to implement GUPSGen which is a
ClockedObject that creates read/write requests to the memory
to update elements in an array. The choosing of elements in
the array follow a random distribution. Each element is read
from and return as GUPSGen implements a key-value store program.
Specifications are found in HPCC website from RandomAccess
benchmark. link below.
https://icl.cs.utk.edu/projectsfiles/hpcc/RandomAccess/

Change-Id: I5c07f230bee317fff2cceec04d15d0218e8ede9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47439
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 22:19:25 +00:00
Matt Sinclair
86e3e52857 tests: add additional space in weekly DNNMark tests
Add space between -c and binary name for all DNNMark tests to conform to
the other tests style and reduce confusion.

Change-Id: I6d0777ba2186f0eedfe7e99db51161106837a624
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51453
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 21:35:02 +00:00
Matt Sinclair
6133ba5f6b tests: fix LULESH weekly regression command
7756c5e added LULESH to the weekly regression script.  However,
it assumed a local installation of gem5-resources which it should
not have.  This commit fixes that so the weekly regression builds the
LULESH binary and then runs it instead.

Change-Id: If91f4340f2d042b0bcb366c5da10f7d0dc5643c5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51207
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 21:34:56 +00:00
Gabe Black
1ee4c4ce43 arch-power: Replace the Loader namespace with loader.
The Loader namespace is deprecated, and is replaced with loader.

Change-Id: Ic973eefd55c6f8a43d3d41346b8b6e4795e19e55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51527
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 20:29:08 +00:00
Gabe Black
8304ed1967 base,arch-arm: Replace Stats namespace with statistics.
The Stats namespace is deprecated.

Change-Id: I17b1aa7fbced5db7b325e5339395281f3b3eda0b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51528
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 20:28:52 +00:00
Gabe Black
4fe9af8d17 mem: Stop using SlavePort as a base class.
There are other classes like "ExternalSlave" which still have the word
"Slave" in them, but at least this will make the build quit complaining
about the deprecated SlavePort.

Change-Id: I917c2880574cb77ea37c69dc2727ac5e84b83cd5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51529
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 20:28:05 +00:00
Gabe Black
2d9e742540 cpu: Stop excluding the protobuf tracer for x86.
Change-Id: I71d9eca4b13809273cdddf8ae175379e382ab9d7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50332
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 20:22:37 +00:00
Gabe Black
ee10eb1cc6 scons: Make the SimObject list from the 'gem5 lib' tag.
Only include SimObject files which match the gem5 lib tag. This way we
can declare SimObjects, and then filter them out based on tags.

Change-Id: I0aca1ef830bcc7beaee80c54d58ba8a188968491
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50331
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 20:22:37 +00:00
Gabe Black
ad944025ab scons,arch: Make the gem5 lib tag imply the current arch tag.
That way you can use the tag to specify when a source file should be
built, instead of conditionally declaring the file to SCons.

Change-Id: Ia3a23860d2ee39ec6b32ee2195648b4d88564c83
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50330
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 20:22:37 +00:00
Gabe Black
79953cf973 scons: Add tag support to ISADesc.
Change-Id: Icac027cc4df48d0a3c06911bd6fa0a8b5b72c60a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50329
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 20:22:37 +00:00
Gabe Black
29705f96ee scons: Add tag support to GdbXml.
Change-Id: I81c015fa8a5cc8f62aeb3f6cc409dc10fd3326e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50328
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 13:13:39 +00:00
Giacomo Travaglini
7260394d4b mem: Make ruby AbstractController compatible with XBar
At the moment the ruby AbstractController is trying to re-send the same
memory request every clock cycle until it finally succeeds [1]
(in other words it is not waiting for a recvReqRetry from the peer
port)

This polling behaviour is not compatible with the gem5 XBar, which is
panicking if it receives two consecutive requests to the same BUSY
layer [2]

This patch is fixing the incompatibility by inhibiting the
AbstractController retry until it gets a notification from the peer
response port

[1]: https://github.com/gem5/gem5/blob/v21.1.0.1/\
    src/mem/ruby/slicc_interface/AbstractController.cc#L303
[2]: https://github.com/gem5/gem5/blob/v21.1.0.1/src/mem/xbar.cc#L196

Change-Id: I0ac38ce286051fb714844de569c2ebf85e71a523
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50367
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 08:45:25 +00:00
Gabe Black
bc1438414a sparc: Stop using fp_enable_check.
SPARC and MIPS are the only ISAs using this mechanism. This is a step
towards making them self sufficient and simplifying the ISA parser, it's
interface to the rest of gem5, and it's assumptions about how ISAs are
structured.

Change-Id: Ied85d5012a806321fd717f654d940171da3450af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48717
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-10-13 07:59:52 +00:00
Gabe Black
645c6b3ceb sparc: Stop special casing FP enable checks for full system.
Set the actual state which gets checked in full system, and then do that
all the time.

Change-Id: I27ea0939ad71f7399b676e22ec2e73e3e0dd6476
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48716
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-10-13 07:59:52 +00:00
Gabe Black
7d92144e1b arch,sparc: Get rid of the unused checkVecEnableFault mechanism.
The method was only defined in SPARC, and SPARC does not use the vector
register file.

Change-Id: I4112eadaecb1f1c6c6db12975bec0cd1fa245d6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48715
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-10-13 07:59:52 +00:00
Giacomo Travaglini
851e543b2f misc: Using OS::off_t in syscall signature
Change-Id: Iefa1e207a3e825959b0fe8df30e6be182d73a0f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51490
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 07:44:00 +00:00
Giacomo Travaglini
37495f8823 misc: Using OS::size_t in syscall signature
Using the host size_t is confusing the guest ABI engine every time
the host and the guest adopt a different data model (ILP32 vs LP64)

For example when a LP64 machine is running an ILP32 application in SE
mode, "size_t" will wrongly inform the guest ABI engine to retrieve the
argument by loading a 64 bit (instead of 32) value from the stack

JIRA: https://gem5.atlassian.net/browse/GEM5-1074

Change-Id: Id7d7740ac429f534a4089331bedf21dc3951bbad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51489
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 07:44:00 +00:00
Giacomo Travaglini
43910b5312 arch-arm: Add ftruncate implementation to the Syscall Table
Change-Id: I27c526c5c8107f888aee7c99b952f086d4fa0e35
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51488
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 07:44:00 +00:00
Giacomo Travaglini
2644cc3cac arch-arm: Add sendto and recvfrom implementations to the Syscall Table
Change-Id: Id3fd65778ad3b5af8ec54381a0b8824115c309f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51487
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 07:44:00 +00:00
Austin Harris
058e4699d8 python: Fix L1 data cache size in cache components
Change-Id: I96119e2a002de3904e87625a3de89abb3cc724a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51452
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 23:32:53 +00:00
Bobby R. Bruce
af73f13ac2 tests: Fix argparse description in simple_binary_run.py
Change-Id: I3a86cf9e3326a06f442315d2510c5aec326af358
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51451
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 23:01:17 +00:00
Gabe Black
9844b9e8cb scons: Rearrange functions to be next to the code that uses them.
The code which generated SimObject related param wrappers, cxx wrappers,
enum headers, etc was organized strangely. All the functions which
were used as SCons Actions were listed next to each other, and then all
the code which would set up each of those types of files and actually
use the Actions were next to each other.

This change rearranges that code so that the Action function is
immediately before the code which applies it. Or in other words, this
section of the SConscript is now grouped by the files being created,
rather than the type of the piece of machinery being defined to do that.

Change-Id: Ideee7bd44dac89c51840ec5970d95f6ccbbd1c8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49402
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-12 22:18:28 +00:00
Gabe Black
3f9b493982 scons: Pull the code which generates debug/flags.cc into a helper script.
Change-Id: Ib4ce51ae0311428e3bcd2dae431cfb0abe185c5d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49401
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 22:18:17 +00:00
Giacomo Travaglini
4fdf61493b mem-ruby: HTMSequencer stats initialized twice
HTMSequencer stats are already initialized in the constructor

This is a bug from:

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/36478

Change-Id: Id7d9b11f45035a46af32584ed86470c65d2a80b6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51407
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 17:58:19 +00:00
Matt Sinclair
c84b22d858 tests: fix square and HeteroSync nightly regression command
Square and HeteroSync's pre-built binaries were downloaded into the
tests folder in the nightly regression script, but the docker
command running them assumed we were in GEM5_ROOT.  This commit
fixes this problem by specificying the benchmark root for the
applications.

Change-Id: I905c8bde7231bc708db01bff196fd85d99c7ceac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51247
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-12 17:02:08 +00:00
Matt Sinclair
96a86780ee dev-hsa,gpu-compute: fix bug with gfx8 VAs for HSA Queues
GFX7 (not supported in gem5) and GFX8 have a bug with how virtual
addresses are calculated for their HSA queues.  The ROCr component of
ROCm solves this problem by doubling the HSA queue size that is
requested, then mapping all virtual addresses in the second half of the
queue to the same virtual addresses as the first half of the queue.
This commit fixes gem5's support to mimic this behavior.

Note that this change does not affect Vega's HSA queue support, because
according to the ROCm documentation, Vega does not have the same problem
as GCN3.

Change-Id: I133cf1acc3a00a0baded0c4c3c2a25f39effdb51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51371
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
2021-10-12 17:01:52 +00:00
Giacomo Travaglini
ac63b7e294 arch-arm: Add fchownat implementation to the Syscall Table
Change-Id: If2e05b84064886bd924348930a151c7c00877c38
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51052
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 15:19:32 +00:00
Giacomo Travaglini
f9a7196396 arch-arm: Add fchown implementation to the Syscall Table
Change-Id: I4696e305383492e3bf3cf079ffb68eac24f6a19d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51051
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 15:19:32 +00:00
Giacomo Travaglini
a4cec05e58 sim-se: Implemnt fchownat syscall
JIRA: https://gem5.atlassian.net/browse/GEM5-1098

Change-Id: I46f9a5ba30a27c29a8a50323a0fb95074016ddb2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51050
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 15:19:32 +00:00
Giacomo Travaglini
b1a2d5f293 arch-arm: Add existing at impl to ArmLinux32 Syscall Table
Change-Id: Ia1e7cb02ce9513e6ef5d7037dafc84fbd52b8504
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51049
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2021-10-12 15:19:32 +00:00
Giacomo Travaglini
528fae6464 sim-se: Implement at suffixed syscalls
All syscalls with the "at" suffix rely on a directory file descriptor
(dirfd) and a pathname, provided as arguments to the syscall

If the pathname is relative, then it is interpreted relative to the
directory referred to by the file descriptor dirfd (rather than relative
to the current working directory of the calling process)

Prior to this patch, only the openat syscall was properly implemented.
Other syscalls were discarding the dirfd argument and producing
a warning instead

JIRA: https://gem5.atlassian.net/browse/GEM5-1098

Change-Id: I0cc20c6ef79fca8c8d1c2c9a52eb54ede3d51312
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51048
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 15:19:32 +00:00
Giacomo Travaglini
8f1f50f410 sim-se: Rewrite some syscalls to use a syscallImpl function
The following at suffixed syscalls are implemented on top of their
CWD version

* readlinkat -> readlink
* unlinkat -> unlink
* renameat -> rename
* faccessat -> access

With this patch we are decoupling interface from implementation, moving
the latter into a separate syscallImpl function which will by called by
both syscall flavours

This is a required step towards properly implementing AT based syscalls

JIRA: https://gem5.atlassian.net/browse/GEM5-1098

Change-Id: I022e9876a2a0b9ddf2d70d10cd4e6851ba7ff094
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51047
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2021-10-12 15:19:32 +00:00
Quentin Forcioli
9854685277 dev-arm: Added trusted DRAM to vexpress Realview
Added the 32MB of trusted DRAM to the VExpress_GEM5_Base Realview.
This trusted DRAM is however not protected against unsecure access.

This commit is part of series of commit to enable booting OPTEE on gem5.

Change-Id: Icbbaec8488dd72e1cbe70015a7f7904de35b38bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49989
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 09:29:50 +00:00
Davide Basilio Bartolini
3d025b517f misc: Fix hdf5 stats + test
HDF5 stats file creation was not completing correctly due to name
clashes.

Change-Id: Ifc2d52f4bbc62b0c6798ce92f4d027b0ec69a373
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51061
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 06:03:21 +00:00
Matt Sinclair
68870342c0 tests: add DNNMark to weekly regression
DNNMark is representative of several simple (fast) layers within ML
applications, which are heavily used in modern GPU applications.  Thus,
we want to make sure support for these applications are tested.  This
commit updates the weekly regression to run three variants: fwd_softmax,
bwd_bn, and fwd_pool -- ensuring we test both inference and training as
well as a variety of ML layers.

Change-Id: I38bfa9bd3a2817099ece46afc2d6132ce346e21a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51187
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-12 00:52:14 +00:00
Gabe Black
66b0497a77 sim: Align process memory allocations.
Align allocation requests in Process::allocateMem to page boundaries,
rather than assume that they already are. This frees the caller from
having to know what boundary to align things to. The older version would
make the caller more aware of the extent of the allocation in theory,
but in reality the caller would just blindly perform the alignment like
this function is anyway.

Change-Id: I897714d4481d961255a9e44ae080135e507be199
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50757
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-11 22:05:28 +00:00
Hoa Nguyen
d4e5d9b32a util: Make gerrit bot respect reviewer removal
Currently, if a maintainer is removed from a change, the maintainer
will be added again. This change prevents the bot from adding the
removed maintainer again.

The bot will query all updates related to reviewer addition/removal
for each new change. If a reviewer has ever been added/removed
from a change, that reviewer won't be added to that change again.

Change-Id: Ifaab5ebd7ebf3e6453b2551d3e37c1b9e214c906
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50187
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-10-11 17:12:59 +00:00
Tom Rollet
13e3521a00 cpu-o3: remove useless 'using'-s
Change-Id: Ifa8ef516d0deabb4308bdf3c4b61b88ece149d0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51347
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-11 08:19:29 +00:00
Tom Rollet
8a535eac48 cpu-o3: Naming cleanup for LSQRequest and Request
'LSQRequest' are now referred as 'request'
'Request' are now referred as 'req'

It makes the code easier to read.
Also it makes the naming of Request consistent with the cache.

Change-Id: I8ba75b75bd8408e411300d522cc2c8582c334cf5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51067
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-10-11 08:19:29 +00:00
Tom Rollet
de0d6f4116 cpu-o3: remove LSQSenderState
The LSQSenderState that was attached to Request was not useful.
All the fields were either a duplicate of information in the
LSQRequest or totally unused.

The LSQRequest class now inherits from Packet::SenderState and is
attached to the Packet that are sent to memory. We do not need
anymore the indirection Packet->SenderState->LSQRequest.

This helps making the code clearer as it was sometimes hard to
follow the difference between what the LSQRequest and
LSQSenserState was doing
(ex: number of outstanding requests in the memory).

Change-Id: I5b21e007e6d183c6aa79c27c1787ca56dcbc3fb0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50733
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-11 08:19:29 +00:00
Matt Sinclair
1120931105 mem-ruby: Move VIPER TCC decrements to action from in_port
Currently, the GPU VIPER TCC protocol handles races between atomics in
the triggerQueue_in.  This in_port does not check for resource
availability, which can cause the trigger queue to execute multiple
times.  Although this is the expected behavior, the code for handling
atomic races decrements the atomicDoneCnt flag in the trigger queue,
which is not safe since resource contention may cause it to execute
multiple times.

To resolve this issue, this commit moves the decrementing of this
counter to a new action that is called in an event that happens only
when the race between atomics is detected.

Change-Id: I552fd4f34fdd9ebeec99fb7aeb4eeb7b150f577f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51368
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-08 22:03:13 +00:00
Matt Sinclair
72ee6d1aad mem-ruby: Update GPU VIPER TCC protocol to resolve deadlock
In the GPU VIPER TCC, programs with mixes of atomics and data
accesses to the same address, in the same kernel, can experience
deadlock when large applications (e.g., Pannotia's graph analytics
algorithms) are running on very small GPUs (e.g., the default 4 CU GPU
configuration).  In this situation, deadlocks occur due to resource
stalls interacting with the behavior of the current implementation for
handling races between atomic accesses.  The specific order of events
causing this deadlock are:

1. TCC is waiting on an atomic to return from directory

2. In the meantime it receives another atomic to the same address -- when
this happens, the TCC increments number of atomics to this address
(numAtomics = 2) that are pending in TBE, and does a write through of the
atomic to the directory.

3. When the first atomic returns from the Directory, it decrements the
numAtomics counter.  numAtomics was at 2 though, because of step #2.  So
it doesn't deallocate the TBE entry and calls Event:AtomicNotDone.

4. Another request (a LD) to the same address comes along for the same
address.  The LD does z_stall since the second atomic is pending –- so the
LD retries every cycle until the deadlock counter times out (or until the
second atomic comes back).

5.  The second atomic returns to the TCC.  However, because there are so
many LD's pending in the cache, all doing z_stall's and retrying every cycle,
there are a lot of resource stalls.  So, when the second atomic returns, it is
forced to retry its operation multiple times -- and each time it decrements
the atomicDoneCnt flag (which was added to catch a race between atomics
arriving and leaving the TCC in 7246f70bfb) repeatedly.  As a result
atomicDoneCnt becomes negative.

6.  Since this atomicDoneCnt flag is used to determine when Event:AtomicDone
happens, and since the resource stalls caused the atomicDoneCnt flag to become
negative, we never complete the atomic.  Which means the pending LD can never
access the line, because it's stuck waiting for the atomic to complete.

7.  Eventually the deadlock threshold is reached.

To fix this issue, this commit changes the VIPER TCC protocol from using
z_stall to using the stall_and_wait buffer method that the
Directory-level of the SLICC already uses.  This change effectively
prevents resource stalls from dominating the TCC level, by putting
pending requests for a given address in a per-address stall buffer.
These requests are then woken up when the pending request returns.

As part of this change, this change also makes two small changes to the
Directory-level protocol (MOESI_AMD_BASE-dir):

1.  Updated the names of the wakeup actions to match the TCC wakeup actions,
to avoid confusion.

2.  Changed transition(B, UnblockWriteThrough, U) to check all stall buffers,
as some requests were being placed later in the stall buffer than was
being checked.  This mirrors the changes in 187c44fe44 to other Directory
transitions to resolve races between GPU and DMA requests, but for
transitions prior workloads did not stress.

Change-Id: I60ac9830a87c125e9ac49515a7fc7731a65723c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51367
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-08 22:03:13 +00:00