Commit Graph

18046 Commits

Author SHA1 Message Date
Bobby R. Bruce
9bc66c5400 arch-gcn3,python: Fix incorrect syntax in ast_interpreter.py
Includes upgrading prints to Python3.

Change-Id: I3349fa6220ad7577b4b4ab9231fb48a8ac4be6fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47020
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-22 20:05:27 +00:00
Bobby R. Bruce
23071cfd8d util,python: Add escape chars to lowp_dram_sweep_ploy.py
Change-Id: I783ddfe0c4c04223527a93af9f367f00544cd300
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47019
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-22 20:05:27 +00:00
Bobby R. Bruce
dd57e9216a mem-ruby: Fix nonsensical check in MOESI_CMP_token-L1cache
This check always equated to False. It should be an 'or' not an 'and'
comparison.

The Clang 11 compiler threw an "overlapping comparisons always evaluate
to false" error for the code generaed from this.

Change-Id: I299dc6fa8206d5e85d59ba8353bf16102b8e5e1b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45799
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45829
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-22 18:18:04 +00:00
Philip Metzler
09b71163be fastmodel: Fix scx_get_parameter_list for ARM fastmodels.
The first non-critical piece of this CL removes the unused self
from the Python function signature.

Then also includes "stl.h" from pybind11 to allow the
implicit conversion from std::map<std::string, std::string>
to a Python dict (otherwise there will be a runtime (not compile time)
error when calling the function.

As the current implementation always throws an error because of the
missing stl.h I don't believe anyone is using this function, and as such
it should be safe to just change the signature of
scx_get_parameter_list.

Change-Id: Ib3202b2d4d1b8418a4adf54739fe389d4ee07743
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45622
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45827
2021-06-22 18:18:04 +00:00
Hoa Nguyen
89dea636c9 util-docker: Use python3 by default for Ubuntu 18.04 docker images
gem5 dropped the support for python2. This change sets python3
to have a higher priority than python2 in the Ubuntu 18.04 docker
images. This is done so that gem5 will be compiled and tested
in the python3 environment by default.

JIRA: https://gem5.atlassian.net/browse/GEM5-958

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I11ffb06697ecf4cebf9f98b611641faa42805547
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45125
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45826
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-06-22 18:18:04 +00:00
Giacomo Travaglini
e6ebda374a configs: restore_simpoint_checkpoint should be a boolean
The --restore_simpoint_checkpoint option is a boolean;
however if no default value is supplied, optparse sets the
default value to None

This is not valid for argparse. Argparse recognizes the store_true
action and it is automatically treating the option as a boolean,
hence providing a default=False instead of default=None

Change-Id: I6b09edf6911be71a06001730be1232a1b5c8482c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44765
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45825
2021-06-22 18:18:04 +00:00
Giacomo Travaglini
33cb1d833b util: Fix cpt_upgrader format string
Change-Id: I9d15316f199b20976420c35d2c79dd13cc9db9ee
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44510
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45824
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-06-22 18:18:04 +00:00
Giacomo Travaglini
7be718a6ef dev: Fix GCN3_X86 builds on aarch64 host
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ic826f0cb46e07b9b5135eee1e518bc13f3d978a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44485
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45823
2021-06-22 18:18:04 +00:00
Yu-hsin Wang
20e2c8da22 systemc: Fix verify.py and make it python 3 compatible
1. The logger behavior change breaks verify.py.
commit 8deb205ea1
Author: Daniel Carvalho <odanrc@yahoo.com.br>
Date:   Wed Mar 3 16:49:05 2021 -0300

    base: Add LOC to Loggers

    Printing the line and the file that triggered a log
    is useful for debugging.

    Change-Id: I74e0637b2943049134bd3e9a4bc6cab3766591a9
    Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
    Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42141
    Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
    Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
    Tested-by: kokoro <noreply+kokoro@google.com>

2. Use bytes diff in LogChecker.
In Python3, string is required to be in a certain encoding, while in Python2,
it is not. In the testcase, misc/cae_test/general/bitwise/or/datatypes,
it contains some invalid codepoint of utf-8, we need diff the log with
bytes in Pyhton3.

3. Python3 compatible.
* dict.iteritems -> dict.items
* remove object base class
* use `except as` when catching exceptions
* handle map and filter behavior change

Test with

src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
  --filter-file src/systemc/tests/working.filt

src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
  --filter-file src/systemc/tests/working.filt --phase verify --result-file

Change-Id: Ibf5b99d08a948387cf6162c476c294c49a7dac0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44465
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45822
2021-06-22 18:18:04 +00:00
Yu-hsin Wang
53da68d661 systemc: Eliminate ClockTick duplicated name warning
In systemc, a module name is consist of hierarchy names with dot
separated. The basename is the last part of the module name. Because
lack of hierarchy information, it's a chance that the basename is
duplicated. Although, ClockTick is using sc_gen_unique_name to solve
this, the warning from sc_gen_unique_name is annoying. To solve this
completely, we should use the full module name to construct the name of
ClockTick.

Change-Id: Ie664fe4757a05f72860be49c3a9d1172f824eb2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44425
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45821
2021-06-22 18:18:04 +00:00
Bobby R. Bruce
5b07a0787b scons: Reverts LTO for opt, perf and prof builds.
This reverts
https://gem5-review.googlesource.com/c/public/gem5/+/40815
and adds the `--with-lto` to enable LTO; and removes `--no-lto`.

Change-Id: I7dbd2b555570c90c98f38c7c02eb052571f7b6bd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44886
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45839
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-22 18:18:04 +00:00
Jason Lowe-Power
935819c37b python,scons: Only generate pybind if using python
This reimplements the previously reverted change: Always generate default
create() methods.

The pybind code should only be generated when python is enabled. This
change passes whether python is enabled into the SimObject code creation
method. Then, the params code is optionally included.

Note: Due to some problems in GCC's linker (or something else...) we
need to have a single file with all of the generated code for the
SimObject.

Change-Id: I0f93b3d787d47f26db2de6c4447730f7df87a0dc
Issue-on: https://gem5.atlassian.net/browse/GEM5-1003
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46880
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-22 18:18:04 +00:00
Jason Lowe-Power
356b4dc476 scons,python: revert Always generate default create() methods.
This reverts commit 7bb690c1ee.

Change-Id: If1b44162b24409fb44daec0159852fa44937184d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46879
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-22 18:18:04 +00:00
Marton Erdos
4e028f8412 cpu-o3: Fix "OldestReady" scheduling bug
Fixed a bug in the SMT scheduling function oldestReady(), where
the oldest sequence number and its thread id were mixed up.

Change-Id: I31df5eac73ecabbe04fb54624ee1b1867fa4d3c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46940
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-22 09:01:42 +00:00
Marton Erdos
8eefaa58af cpu-o3: Removed "Aggressive" SMT scheduling option
A comment claimed this to be different from "oldestReady", when in fact
it was not. Removed it for clarity.

Change-Id: Ic66ee9974ddc8d7a01929afabb601473b7ea23ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46939
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-22 09:01:42 +00:00
Bobby R. Bruce
4b7e67b151 base,tests: Fix trace.test.cc for .fast
Due to DPRINTFs compiling in all cases:
https://gem5-review.googlesource.com/c/public/gem5/+/44988,
trace.test.cc failed to compile for the .fast build (`scons
build/NULL/unittests.fast`). This patch fixes this by moving the
DPRINTFs into the `TRACING_ON` compile guards.

Change-Id: Ib37b2d90f19b9dbc1503941d69d5a2dc0c1c9d9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46959
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-18 17:48:53 +00:00
Daniel R. Carvalho
499a1cc7e8 base-stats,mem: Fix empty Stats::Info names
Sub-groups should not contain empty names. To make sure
that is the case, generate tokens even if the string is
empty.

Before the name 'group1..group2' would generate 2 tokens:
'group1' and 'group2'. As such, validateStatName would
not be able to detect it was an invalid name. With this
change three tokens will be generated: 'group1', '',
and 'group2'. The empty string will then trigger the
item->empty() check, which will successfully inform that
such stat name is not valid.

SLICC was breaking this rule with one of its stats by
creating a sub-group (inTransLatHist) whose parent had
an empty name, so it has been fixed.

Change-Id: Ica5ca684911374d59a0a809636594d048d755deb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43590
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-17 21:09:51 +00:00
Daniel R. Carvalho
cdc5758b51 base: Document the SymbolTable
Add Doxygen documentation to SymbolTable's contents.
Some parameters were renamed to make their purpose
easier to understand.

Change-Id: Ia4f18bf60d3d8eab7a775f34f553d420816d62b9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43248
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-17 21:09:51 +00:00
Daniel R. Carvalho
f43febb218 base-stats: Fix null addStatGroup
A group must be provided to be added to a stat
group.

Change-Id: I9da42fb12c2a8b258f9f45922a6fb6b7fd41a698
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43012
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-17 21:09:51 +00:00
Daniel R. Carvalho
af2d420b42 base-stats: Fix self addition bug in addStatGroup
A group cannot be added to itself; otherwise, it would
create a cyclic dependency.

Change-Id: I2e42f84814c675e8d5318cfda2d99b1b394758aa
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43011
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-17 21:09:51 +00:00
Daniel R. Carvalho
71653e20fb base-stats: Remove Stats::Group dependency from Stats::Info
The parent group was not being used. The only thing required
was the information of whether the info concerns a new or an
old-style stats. Removing this dependency simplifies code
and removes a possible cyclic dependency.

Change-Id: I4d734cd83e9c7975a3ef45229edea4eebf1e430e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43589
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-17 21:09:51 +00:00
Daniel R. Carvalho
f5204295b1 base-stats: Remove SimObject dependency from stats group
Remove this circular dependency by casting to Named
instead of SimObject.

Change-Id: I1054562750ba30d3ad4f9e2fbe238fd6fe2d4cb0
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43005
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-17 21:09:51 +00:00
Daniel R. Carvalho
a1a71a128d sim: Remove SimObject dependency from Drainable
Remove this circular dependency by casting to Named
instead of SimObject.

Change-Id: Ia064f7ab1a693586b6bd0045f431512ca3c78801
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43004
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-17 21:09:51 +00:00
Daniel R. Carvalho
a906e04cb7 sim: Make SimObject inherit from Named
Standardize name creation of sim objects.

Change-Id: I5e0cb828da0810b47217e96e302857e32083c50b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43246
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-17 21:09:51 +00:00
Daniel R. Carvalho
bac49a04b5 base: Make Named::name() non-reference
Some of the use cases for name() inheritance may
use local strings, which complicates the use of
rvalues.

Change-Id: I22188a238dbe73a5f174f70b88bc4b8812f9d31a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43588
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-17 21:09:51 +00:00
Daniel R. Carvalho
ad5ae10c8e base: Make Named::name() virtual
Allow inherited classes to modify the defaul behavior
of name(). This can be useful, for example, when the
class names relies on sub-modules' names.

Change-Id: I6a4bc0cd13ca05e75557ed90b12a6bd6708925ec
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43245
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-17 21:09:51 +00:00
Daniel R. Carvalho
5f0e38bab0 sim: Add missing compiler include
Add missing base/compiler.hh include for the
namespace deprecation macro.

Change-Id: I43fad575fa538be2bef5296938b71ed8eded2ecf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46919
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-17 13:45:35 +00:00
Daniel R. Carvalho
94d44ada63 sim: Add unit test for sim/port
Add a unit test for sim/port.

The fact that binding a port does not automatically
bind its peer is error-prone, and should likely be
revisited in the future.

Change-Id: Iee91fc9bfa80a527d9a1902529722833b061dec9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43003
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-16 10:50:26 +00:00
Daniel R. Carvalho
7f5bd15f51 base: Add unit test for base/trace.hh
Add an unit test for base/trace.hh.

Marked the source files needed for tracing with a 'gem5 trace'
tag.

Change-Id: Ib1e17de3c772146596a26a2ce5aa7a6310bf7938
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41336
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-16 10:50:26 +00:00
Daniel R. Carvalho
43f3c51bce sim: Make IniFile non-pointer in CheckpointIn
There is no need to use a pointer for this variable.

Change-Id: I784c94c8b775880def8339df63540357c2078c7b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38741
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-16 10:50:26 +00:00
Daniel R. Carvalho
05c0d52370 sim: Remove SimObject dependency from serialize.hh
Previously Serializable::serializeAll called SimObject::
serializeAll. This created an unnecessary dependency. This
change makes Serializable responsible for the generation
of the checkpoint file, and then the SimObjects will
perform the serialization of the object using that file.

With this change serialize.hh contains only functions
related to the (un)serialization of basic types or
objects that inherit from Serializable. As a general
rule, functions related to the (un)serialization of
specific/other types must be defined in the file that
introduces that type.

Change-Id: I9438b799d7e9d4c992a62c7f9d1f15f3f3250a5a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38740
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-06-16 10:50:26 +00:00
Daniel R. Carvalho
18de63cea0 sim: Remove (UN)SERIALIZE_OBJ_PTR
SimObjects keep a static list with all existing
SimObjects. This list is then used to serialize
all objects declared in the system. If these
macros were used then an object would be serialized
more than once, which is not a correct behavior.

Change-Id: Idc4433ec2a23a21ee5ee2b7cc2facfe3dd979859
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46720
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-06-16 10:50:26 +00:00
Daniel R. Carvalho
19c7429520 sim,util: Remove event dependencies from serialize.hh
With this change serialize.hh is no longer responsible
for the (un)serialization of events. As a general rule,
rules to (un)serialize non-basic types should be defined
at the file that introduces that type. Therefore,
(UN)SERIALIZE_EVENT have been moved to eventq.hh.

Globals has a single instance which must be serialized
and unserialized. Instead of having a stray global
variable handled by Serialization, we pass its management
to Root. As a side effect, Globals is assigned its own
files: sim/globals.(cc/hh).

Finally, 'unserializeGlobals()' is removed, so that
Root can fully handle Globals' serialization. This
breaks checkpoint compatibility, so a checkpoint
upgrader is added.

Change-Id: I9c8e57306f83f9cc30ab2b745a4972755191bec4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43586
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-06-16 10:50:26 +00:00
Matthew Poremba
c493d2c4ad sim,mem-ruby: Handle interleaved device memory
Device memories are used for PCI devices which have their own pools of
backing store memory such as amdgpu device. The check for an address
being in device memory previously did not handle multiple interleaved
memory devices with the same address range. Therefore, the device memory
check would fail if the interleaving masks did not match. This updates
the method to iterate through all device memories that handle the
RequestorID and returns true if any of the device memories contain the
packet address.

Change-Id: I9339d39c1cb54a5b9075c4a122c118fe61dc6fdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46381
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-14 15:48:51 +00:00
sacak32
b0f534346a mem-cache: queued prefetcher bug fix
In queued prefetcher, addToQueue function doesn't behave
correctly where the element must be added to the end of queue.
I fixed this bug.

Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Signed-off-by: Burak Öçalan <byrakocalan99@gmail.com>
Reported-by: Burak Öçalan <byrakocalan99@gmail.com>
Tested-by: Burak Öçalan <byrakocalan99@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46759
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-12 08:21:04 +00:00
Daniel R. Carvalho
6977456207 util: Fix typo in cpt upgrader
The module is errno, not ennro.

Change-Id: I3f17bdc12a7acd680ac407042a75d5099f5f7339
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46799
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-11 18:42:13 +00:00
Matthew Poremba
3adefc2dd9 dev-amdgpu: Handle framebuffer counter accesses
There are special counters in the framebuffer that are tested during
driver initialization. The expected behavior of the counters is to
return the previously read value + 1. There is one (known) counter used
in driver initialization at a fixed BAR address offset.

Change-Id: Id2dbb5fa9365b0a0453b15013c45aa67a2eec190
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46163
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-06-11 17:10:32 +00:00
Matthew Poremba
f46c9ddbfb util: Add scripts to recreate amdgpu ROM and MMIOs
Although the binary ROM blob and MMIO trace will be placed in
gem5-resources later as 'golden' versions, the scripts are added to
provide instructions for power users of Full System amdgpu that may want
to recreate the files themselves or use a GPU other than the Vega10 GPU
currently modeled.

Change-Id: Ica7ef3b9820b30be32a148ce6cf1d2f81dc2adf9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46162
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-06-11 17:10:32 +00:00
Matthew Poremba
e9bac9df87 dev-amdgpu,configs: checkpoint before MMIOs
The flow for Full System amdgpu is the use KVM to boot linux and begin
loading the driver module. However, the amdgpu module requires reading
the VGA ROM located at 0xc0000 in X86. KVM does not support having a
small 128KiB hole at this location, therefore we take a checkpoint and
switch to a timing CPU to continue loading the drivers before the VGA
ROM is read.

This creates a checkpoint just before the first MMIOs. This is indicated
by three interrupts being sent to the PCI device. After three interrupts
in a row are counted a checkpoint exit event occurs. The interrupt
counter is reset if a non-interrupt PCI read is seen.

Change-Id: I23b320abe81ff6e766cb3f604eca2979339938e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46161
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-11 17:10:32 +00:00
Matthew Poremba
7426a0da8e dev-amdgpu: Implement MMIO trace reader
Helper class to read Linux kernel MMIO trace from amdgpu modprobes. This
class is used rather than implementing MMIOs in code as it is easier to
update to newer kernel versions this way. It also helps with setting
values for registers which are not documented.

Based on https://gem5-review.googlesource.com/c/amd/gem5/+/23743

Change-Id: Ia9b85c269c98b6ae0d5bcfe89141a4c30ef2f914
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46160
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-11 17:10:32 +00:00
Matthew Poremba
ca12a8997d mem-ruby,sim: Add support for VGA ROM memory region
Checks if the address is in a shadowed region, and sends the request
to pio to be serviced by the device backing up that range.

Based on: https://gem5-review.googlesource.com/c/amd/gem5/+/23484

Change-Id: I4d5b46cccd6203523008b2e9545d55eb62130964
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46159
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-11 17:10:32 +00:00
Giacomo Travaglini
182ef827c8 cpu: Implement basic HTM capabilities in the CheckerCPU
The O3CPU, which supports transactional memory (HTM), is using
the inHtmTransactionalState and getHtmCheckpointPtr methods
to check if we are in the middle of a transaction and return
false or a nullptr if that's not the case.

We need to avoid aborting simulation (panic) when those methods are
called in the O3CPU + Checker simulation.

This patch is providing the minimal support to re-enable O3 + Checker
runs and it is not providing HTM support in the CheckerCPU (meaning, we
won't be able to use the Checker in a transactional simulation)

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I7f71d5290c53b0402763d69f137ecaa1208253fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46624
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-11 08:49:27 +00:00
Bobby R. Bruce
0249cb0107 tests: Add nightly tests script to the gem5 repo
This script previously existed entirely within our Jenkins instance.
However, in the interests of transparancy, and allowing users to run the
Nightly tests on their own machines, this script should be added to the
repo. This also allows the community to change the nightly tests without
contacting the Jenkins' administrators.

Change-Id: I6cc3d7597776dbdeb9efb31766d579a2be733d68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46520
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-10 17:59:15 +00:00
Bobby R. Bruce
43ac896c9d tests: Move compiler-tests.sh script from "util" to "tests"
Change-Id: I69ccafc2a944a72e502a702d829c75e8ebfa7e13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46519
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-10 17:59:15 +00:00
Giacomo Travaglini
10bb6b076a arch-arm: Remove the TLB::flush overload for TLBI IPA
This will be handled by the MMU

Change-Id: I2cc2cae2a742f3c795867b7b85826e482cacc888
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45782
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-06-10 08:01:01 +00:00
Giacomo Travaglini
af1e8667e1 arch-arm: Remove stage2 TLBI flushes from stage1 flushes
This is not needed anymore as stage2 flush is now handled by
the MMU. With this patch we are progressively removing any link
between stage1 and stage2 TLBs

Change-Id: I3e9e339a78ac972bc536214152f6c68d6a50cb5c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45781
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-10 08:01:01 +00:00
Giacomo Travaglini
31b37a7f73 cpu: Register the ThreadContext in the CheckerCPU's ISA
This is needed after [1], as the Checker's ISA has an invalid (nullptr)
TC pointer.

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/29233

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I1d25096caf61f98451fca2d393d2ea1c4fca00e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46623
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-10 08:00:07 +00:00
Giacomo Travaglini
5d6bb698f2 cpu: Do not generate a DTB node in the CheckerCPU
The CheckerCPU is not a real CPU and shouldn't generate a DTB
node. This is why we are skipping the BaseCPU implementation
and we are calling the base SimObject one.

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I42326be9d4c440846fdf8d43bf809ad4d50f61d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46622
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-10 08:00:07 +00:00
Giacomo Travaglini
f1fd8cf747 cpu: Fix MMU port addition from the CheckerCPU
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I596eb74faa2226e49f195c6c178e296f5eca7d37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46621
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-10 08:00:07 +00:00
Giacomo Travaglini
7a5585ef51 cpu: Fix import in O3 CheckerCPU
ArmMMU isn't defined in ArmTLB

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Idc33720303d20cf6176e6ec6d17197661526eb2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46620
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-10 08:00:07 +00:00