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arch-riscv: Revert CSR instruction fixes

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This reverts commit 4b1c245420
and commit 89c49d1ab0 because
they are causing the RISC-V Ubuntu boot test within the
nightly tests to hang and time out.

Change-Id: Ia4d8098ec940cb5900256c8cede0146256c851e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68637
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Roger Chang <rogerycchang@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Melissa Jost
2023-03-03 17:24:58 -08:00
committed by Melissa Jost
parent da050eedde
commit fd7006f4f1
2 changed files with 8 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/arch/riscv/insts/standard.hh
View File

@@ -91,33 +91,18 @@ class CSROp : public RiscvStaticInst
protected:
uint64_t csr;
uint64_t uimm;
bool read;
bool write;
/// Constructor
CSROp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass),
csr(FUNCT12), uimm(CSRIMM), read(true), write(true)
csr(FUNCT12), uimm(CSRIMM)
{
if (csr == CSR_SATP) {
flags[IsSquashAfter] = true;
}
if (strcmp(mnemonic, "csrrw") == 0 ||
strcmp(mnemonic, "csrrwi") == 0) {
if (RD == 0){
read = false;
}
} else if (strcmp(mnemonic, "csrrs") == 0 ||
strcmp(mnemonic, "csrrc") == 0 ||
strcmp(mnemonic, "csrrsi") == 0 ||
strcmp(mnemonic, "csrrci") == 0 ){
if (RS1 == 0 || uimm == 0) {
write = false;
}
}
}
std::string generateDisassembly(
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
};

15
src/arch/riscv/isa/formats/standard.isa
View File

@@ -358,7 +358,7 @@ def template CSRExecute {{
%(op_decl)s;
%(op_rd)s;
RegVal data = 0, olddata = 0, nonmaskdata = 0;
RegVal data, olddata;
auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8);
auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
if (pm < lowestAllowedMode) {
@@ -380,13 +380,11 @@ def template CSRExecute {{
break;
}
if (read) {
if (csr == CSR_FCSR) {
if (csr == CSR_FCSR) {
olddata = xc->readMiscReg(MISCREG_FFLAGS) |
(xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
} else {
(xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
} else {
olddata = xc->readMiscReg(midx);
}
}
olddata = rvZext(olddata);
auto olddata_all = olddata;
@@ -397,9 +395,8 @@ def template CSRExecute {{
%(code)s;
nonmaskdata = data & ~maskVal;
data &= maskVal;
if (write) {
if (data != olddata) {
if (bits(csr, 11, 10) == 0x3) {
return std::make_shared<IllegalInstFault>(
csprintf("CSR %s is read-only\n", csrName), machInst);
@@ -420,7 +417,7 @@ def template CSRExecute {{
case CSR_SIP: case CSR_SIE:
case CSR_UIP: case CSR_UIE:
case CSR_MSTATUS: case CSR_SSTATUS: case CSR_USTATUS:
if (nonmaskdata == 0) {
if (newdata_all != olddata_all) {
xc->setMiscReg(midx, newdata_all);
} else {
return std::make_shared<IllegalInstFault>(