From fd7006f4f1a34d6bbfe0c7d62be72ced43281462 Mon Sep 17 00:00:00 2001 From: Melissa Jost Date: Fri, 3 Mar 2023 17:24:58 -0800 Subject: [PATCH] arch-riscv: Revert CSR instruction fixes This reverts commit 4b1c24542065380c6cff7ab2baa25e216a0ad38e and commit 89c49d1ab06ea5364ab1f80586f8b01c0297cb12 because they are causing the RISC-V Ubuntu boot test within the nightly tests to hang and time out. Change-Id: Ia4d8098ec940cb5900256c8cede0146256c851e5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68637 Tested-by: kokoro Reviewed-by: Roger Chang Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power --- src/arch/riscv/insts/standard.hh | 19 ++----------------- src/arch/riscv/isa/formats/standard.isa | 15 ++++++--------- 2 files changed, 8 insertions(+), 26 deletions(-) diff --git a/src/arch/riscv/insts/standard.hh b/src/arch/riscv/insts/standard.hh index 2dfe73aedf..5b0e8c2c22 100644 --- a/src/arch/riscv/insts/standard.hh +++ b/src/arch/riscv/insts/standard.hh @@ -91,33 +91,18 @@ class CSROp : public RiscvStaticInst protected: uint64_t csr; uint64_t uimm; - bool read; - bool write; /// Constructor CSROp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : RiscvStaticInst(mnem, _machInst, __opClass), - csr(FUNCT12), uimm(CSRIMM), read(true), write(true) + csr(FUNCT12), uimm(CSRIMM) { if (csr == CSR_SATP) { flags[IsSquashAfter] = true; } - if (strcmp(mnemonic, "csrrw") == 0 || - strcmp(mnemonic, "csrrwi") == 0) { - if (RD == 0){ - read = false; - } - } else if (strcmp(mnemonic, "csrrs") == 0 || - strcmp(mnemonic, "csrrc") == 0 || - strcmp(mnemonic, "csrrsi") == 0 || - strcmp(mnemonic, "csrrci") == 0 ){ - if (RS1 == 0 || uimm == 0) { - write = false; - } - } } - std::string generateDisassembly( + std::string generateDisassembly( Addr pc, const loader::SymbolTable *symtab) const override; }; diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index c94a0bcdbd..bb500f5f49 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -358,7 +358,7 @@ def template CSRExecute {{ %(op_decl)s; %(op_rd)s; - RegVal data = 0, olddata = 0, nonmaskdata = 0; + RegVal data, olddata; auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8); auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV); if (pm < lowestAllowedMode) { @@ -380,13 +380,11 @@ def template CSRExecute {{ break; } - if (read) { - if (csr == CSR_FCSR) { + if (csr == CSR_FCSR) { olddata = xc->readMiscReg(MISCREG_FFLAGS) | - (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET); - } else { + (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET); + } else { olddata = xc->readMiscReg(midx); - } } olddata = rvZext(olddata); auto olddata_all = olddata; @@ -397,9 +395,8 @@ def template CSRExecute {{ %(code)s; - nonmaskdata = data & ~maskVal; data &= maskVal; - if (write) { + if (data != olddata) { if (bits(csr, 11, 10) == 0x3) { return std::make_shared( csprintf("CSR %s is read-only\n", csrName), machInst); @@ -420,7 +417,7 @@ def template CSRExecute {{ case CSR_SIP: case CSR_SIE: case CSR_UIP: case CSR_UIE: case CSR_MSTATUS: case CSR_SSTATUS: case CSR_USTATUS: - if (nonmaskdata == 0) { + if (newdata_all != olddata_all) { xc->setMiscReg(midx, newdata_all); } else { return std::make_shared(