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Merge branch 'develop' into mypy-1.8.0

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This commit is contained in:
Bobby R. Bruce
2024-02-02 10:40:50 -08:00
committed by GitHub
parent 80a7dfc300 ea3face87b
commit f0ee1db19f
20 changed files with 855 additions and 1035 deletions
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4
.github/workflows/daily-tests.yaml vendored
View File

@@ -285,7 +285,7 @@ jobs:
- name: Get Square test-prog from gem5-resources
uses: wei/wget@v1
with:
args: -q https://dist.gem5.org/dist/v24-0/test-progs/square/square # Removed -N bc it wasn't available within actions, should be okay bc workspace is clean every time: https://github.com/coder/sshcode/issues/102
args: -q http://dist.gem5.org/dist/v24-0/test-progs/square/square # Removed -N bc it wasn't available within actions, should be okay bc workspace is clean every time: https://github.com/coder/sshcode/issues/102
- name: Run Square test with VEGA_X86/gem5.opt (SE mode)
run: |
mkdir -p tests/testing-results
@@ -293,7 +293,7 @@ jobs:
- name: Get allSyncPrims-1kernel from gem5-resources
uses: wei/wget@v1
with:
args: -q https://dist.gem5.org/dist/v24-0/test-progs/heterosync/allSyncPrims-1kernel # Removed -N bc it wasn't available within actions, should be okay bc workspace is clean every time
args: -q http://dist.gem5.org/dist/v24-0/test-progs/heterosync/allSyncPrims-1kernel # Removed -N bc it wasn't available within actions, should be okay bc workspace is clean every time
- name: Run allSyncPrims-1kernel sleepMutex test with VEGA_X86/gem5.opt (SE mode)
run: ./build/VEGA_X86/gem5.opt configs/example/apu_se.py --reg-alloc-policy=dynamic -n3 -c allSyncPrims-1kernel --options="sleepMutex 10 16
4"

2
requirements.txt
View File

@@ -1,2 +1,2 @@
mypy==1.8.0
pre-commit==2.20.0
pre-commit==3.6.0

62
src/arch/arm/insts/misc.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2013, 2017-2018, 2021 Arm Limited
* Copyright (c) 2010, 2012-2013, 2017-2018, 2021, 2023 Arm Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -411,7 +411,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIALL tlbiOp(EL1, secure);
TLBIALL tlbiOp(TranslationRegime::EL10, secure);
tlbiOp(tc);
return;
}
@@ -421,7 +421,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIALL tlbiOp(EL1, secure);
TLBIALL tlbiOp(TranslationRegime::EL10, secure);
tlbiOp.broadcast(tc);
return;
}
@@ -431,7 +431,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
ITLBIALL tlbiOp(EL1, secure);
ITLBIALL tlbiOp(TranslationRegime::EL10, secure);
tlbiOp(tc);
return;
}
@@ -441,7 +441,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
DTLBIALL tlbiOp(EL1, secure);
DTLBIALL tlbiOp(TranslationRegime::EL10, secure);
tlbiOp(tc);
return;
}
@@ -451,7 +451,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVA tlbiOp(EL1,
TLBIMVA tlbiOp(TranslationRegime::EL10,
secure,
mbits(value, 31, 12),
bits(value, 7, 0),
@@ -466,7 +466,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVA tlbiOp(EL1,
TLBIMVA tlbiOp(TranslationRegime::EL10,
secure,
mbits(value, 31, 12),
bits(value, 7, 0),
@@ -481,7 +481,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVA tlbiOp(EL1,
TLBIMVA tlbiOp(TranslationRegime::EL10,
secure,
mbits(value, 31, 12),
bits(value, 7, 0),
@@ -496,7 +496,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVA tlbiOp(EL1,
TLBIMVA tlbiOp(TranslationRegime::EL10,
secure,
mbits(value, 31, 12),
bits(value, 7, 0),
@@ -511,7 +511,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIASID tlbiOp(EL1,
TLBIASID tlbiOp(TranslationRegime::EL10,
secure,
bits(value, 7, 0));
@@ -524,7 +524,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIASID tlbiOp(EL1,
TLBIASID tlbiOp(TranslationRegime::EL10,
secure,
bits(value, 7, 0));
@@ -537,7 +537,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVAA tlbiOp(EL1, secure,
TLBIMVAA tlbiOp(TranslationRegime::EL10, secure,
mbits(value, 31, 12), false);
tlbiOp(tc);
@@ -549,7 +549,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVAA tlbiOp(EL1, secure,
TLBIMVAA tlbiOp(TranslationRegime::EL10, secure,
mbits(value, 31, 12), true);
tlbiOp(tc);
@@ -561,7 +561,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVAA tlbiOp(EL1, secure,
TLBIMVAA tlbiOp(TranslationRegime::EL10, secure,
mbits(value, 31, 12), false);
tlbiOp.broadcast(tc);
@@ -573,7 +573,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVAA tlbiOp(EL1, secure,
TLBIMVAA tlbiOp(TranslationRegime::EL10, secure,
mbits(value, 31, 12), true);
tlbiOp.broadcast(tc);
@@ -585,7 +585,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVAA tlbiOp(EL2, secure,
TLBIMVAA tlbiOp(TranslationRegime::EL2, secure,
mbits(value, 31, 12), false);
tlbiOp(tc);
@@ -597,7 +597,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVAA tlbiOp(EL2, secure,
TLBIMVAA tlbiOp(TranslationRegime::EL2, secure,
mbits(value, 31, 12), true);
tlbiOp(tc);
@@ -609,7 +609,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVAA tlbiOp(EL2, secure,
TLBIMVAA tlbiOp(TranslationRegime::EL2, secure,
mbits(value, 31, 12), false);
tlbiOp.broadcast(tc);
@@ -621,7 +621,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIMVAA tlbiOp(EL2, secure,
TLBIMVAA tlbiOp(TranslationRegime::EL2, secure,
mbits(value, 31, 12), true);
tlbiOp.broadcast(tc);
@@ -633,7 +633,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIIPA tlbiOp(EL1,
TLBIIPA tlbiOp(TranslationRegime::EL10,
secure,
static_cast<Addr>(bits(value, 35, 0)) << 12,
false);
@@ -648,7 +648,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIIPA tlbiOp(EL1,
TLBIIPA tlbiOp(TranslationRegime::EL10,
secure,
static_cast<Addr>(bits(value, 35, 0)) << 12,
true);
@@ -663,7 +663,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIIPA tlbiOp(EL1,
TLBIIPA tlbiOp(TranslationRegime::EL10,
secure,
static_cast<Addr>(bits(value, 35, 0)) << 12,
false);
@@ -678,7 +678,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
TLBIIPA tlbiOp(EL1,
TLBIIPA tlbiOp(TranslationRegime::EL10,
secure,
static_cast<Addr>(bits(value, 35, 0)) << 12,
true);
@@ -692,7 +692,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
ITLBIMVA tlbiOp(EL1,
ITLBIMVA tlbiOp(TranslationRegime::EL10,
secure,
mbits(value, 31, 12),
bits(value, 7, 0));
@@ -706,7 +706,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
DTLBIMVA tlbiOp(EL1,
DTLBIMVA tlbiOp(TranslationRegime::EL10,
secure,
mbits(value, 31, 12),
bits(value, 7, 0));
@@ -720,7 +720,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
ITLBIASID tlbiOp(EL1,
ITLBIASID tlbiOp(TranslationRegime::EL10,
secure,
bits(value, 7, 0));
@@ -733,7 +733,7 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
bool secure = release->has(ArmExtension::SECURITY) && !scr.ns;
DTLBIASID tlbiOp(EL1,
DTLBIASID tlbiOp(TranslationRegime::EL10,
secure,
bits(value, 7, 0));
@@ -743,28 +743,28 @@ TlbiOp::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
// TLB Invalidate All, Non-Secure Non-Hyp
case MISCREG_TLBIALLNSNH:
{
TLBIALLN tlbiOp(EL1);
TLBIALLN tlbiOp(TranslationRegime::EL10);
tlbiOp(tc);
return;
}
// TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
case MISCREG_TLBIALLNSNHIS:
{
TLBIALLN tlbiOp(EL1);
TLBIALLN tlbiOp(TranslationRegime::EL10);
tlbiOp.broadcast(tc);
return;
}
// TLB Invalidate All, Hyp mode
case MISCREG_TLBIALLH:
{
TLBIALLN tlbiOp(EL2);
TLBIALLN tlbiOp(TranslationRegime::EL2);
tlbiOp(tc);
return;
}
// TLB Invalidate All, Hyp mode, Inner Shareable
case MISCREG_TLBIALLHIS:
{
TLBIALLN tlbiOp(EL2);
TLBIALLN tlbiOp(TranslationRegime::EL2);
tlbiOp.broadcast(tc);
return;
}

498
src/arch/arm/insts/misc64.cc
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File diff suppressed because it is too large Load Diff

126
src/arch/arm/isa/formats/aarch64.isa
View File

@@ -531,27 +531,27 @@ namespace Aarch64
case MISCREG_TLBI_ALLE1:
case MISCREG_TLBI_VMALLS12E1:
case MISCREG_TLBI_VMALLE1:
case MISCREG_TLBI_VAE3_Xt:
case MISCREG_TLBI_VALE3_Xt:
case MISCREG_TLBI_VAE2_Xt:
case MISCREG_TLBI_VALE2_Xt:
case MISCREG_TLBI_VAE1_Xt:
case MISCREG_TLBI_VALE1_Xt:
case MISCREG_TLBI_ASIDE1_Xt:
case MISCREG_TLBI_VAAE1_Xt:
case MISCREG_TLBI_VAALE1_Xt:
case MISCREG_TLBI_IPAS2E1_Xt:
case MISCREG_TLBI_IPAS2LE1_Xt:
case MISCREG_TLBI_RVAE1_Xt:
case MISCREG_TLBI_RVAAE1_Xt:
case MISCREG_TLBI_RVALE1_Xt:
case MISCREG_TLBI_RVAALE1_Xt:
case MISCREG_TLBI_RIPAS2E1_Xt:
case MISCREG_TLBI_RIPAS2LE1_Xt:
case MISCREG_TLBI_RVAE2_Xt:
case MISCREG_TLBI_RVALE2_Xt:
case MISCREG_TLBI_RVAE3_Xt:
case MISCREG_TLBI_RVALE3_Xt:
case MISCREG_TLBI_VAE3:
case MISCREG_TLBI_VALE3:
case MISCREG_TLBI_VAE2:
case MISCREG_TLBI_VALE2:
case MISCREG_TLBI_VAE1:
case MISCREG_TLBI_VALE1:
case MISCREG_TLBI_ASIDE1:
case MISCREG_TLBI_VAAE1:
case MISCREG_TLBI_VAALE1:
case MISCREG_TLBI_IPAS2E1:
case MISCREG_TLBI_IPAS2LE1:
case MISCREG_TLBI_RVAE1:
case MISCREG_TLBI_RVAAE1:
case MISCREG_TLBI_RVALE1:
case MISCREG_TLBI_RVAALE1:
case MISCREG_TLBI_RIPAS2E1:
case MISCREG_TLBI_RIPAS2LE1:
case MISCREG_TLBI_RVAE2:
case MISCREG_TLBI_RVALE2:
case MISCREG_TLBI_RVAE3:
case MISCREG_TLBI_RVALE3:
return new Tlbi64LocalHub(
machInst, miscReg, rt);
case MISCREG_TLBI_ALLE3IS:
@@ -564,48 +564,48 @@ namespace Aarch64
case MISCREG_TLBI_VMALLS12E1OS:
case MISCREG_TLBI_VMALLE1IS:
case MISCREG_TLBI_VMALLE1OS:
case MISCREG_TLBI_VAE3IS_Xt:
case MISCREG_TLBI_VAE3OS_Xt:
case MISCREG_TLBI_VALE3IS_Xt:
case MISCREG_TLBI_VALE3OS_Xt:
case MISCREG_TLBI_VAE2IS_Xt:
case MISCREG_TLBI_VAE2OS_Xt:
case MISCREG_TLBI_VALE2IS_Xt:
case MISCREG_TLBI_VALE2OS_Xt:
case MISCREG_TLBI_VAE1IS_Xt:
case MISCREG_TLBI_VAE1OS_Xt:
case MISCREG_TLBI_VALE1IS_Xt:
case MISCREG_TLBI_VALE1OS_Xt:
case MISCREG_TLBI_ASIDE1IS_Xt:
case MISCREG_TLBI_ASIDE1OS_Xt:
case MISCREG_TLBI_VAAE1IS_Xt:
case MISCREG_TLBI_VAAE1OS_Xt:
case MISCREG_TLBI_VAALE1IS_Xt:
case MISCREG_TLBI_VAALE1OS_Xt:
case MISCREG_TLBI_IPAS2E1IS_Xt:
case MISCREG_TLBI_IPAS2E1OS_Xt:
case MISCREG_TLBI_IPAS2LE1IS_Xt:
case MISCREG_TLBI_IPAS2LE1OS_Xt:
case MISCREG_TLBI_RVAE1IS_Xt:
case MISCREG_TLBI_RVAE1OS_Xt:
case MISCREG_TLBI_RVAAE1IS_Xt:
case MISCREG_TLBI_RVAAE1OS_Xt:
case MISCREG_TLBI_RVALE1IS_Xt:
case MISCREG_TLBI_RVALE1OS_Xt:
case MISCREG_TLBI_RVAALE1IS_Xt:
case MISCREG_TLBI_RVAALE1OS_Xt:
case MISCREG_TLBI_RIPAS2E1IS_Xt:
case MISCREG_TLBI_RIPAS2E1OS_Xt:
case MISCREG_TLBI_RIPAS2LE1IS_Xt:
case MISCREG_TLBI_RIPAS2LE1OS_Xt:
case MISCREG_TLBI_RVAE2IS_Xt:
case MISCREG_TLBI_RVAE2OS_Xt:
case MISCREG_TLBI_RVALE2IS_Xt:
case MISCREG_TLBI_RVALE2OS_Xt:
case MISCREG_TLBI_RVAE3IS_Xt:
case MISCREG_TLBI_RVAE3OS_Xt:
case MISCREG_TLBI_RVALE3IS_Xt:
case MISCREG_TLBI_RVALE3OS_Xt:
case MISCREG_TLBI_VAE3IS:
case MISCREG_TLBI_VAE3OS:
case MISCREG_TLBI_VALE3IS:
case MISCREG_TLBI_VALE3OS:
case MISCREG_TLBI_VAE2IS:
case MISCREG_TLBI_VAE2OS:
case MISCREG_TLBI_VALE2IS:
case MISCREG_TLBI_VALE2OS:
case MISCREG_TLBI_VAE1IS:
case MISCREG_TLBI_VAE1OS:
case MISCREG_TLBI_VALE1IS:
case MISCREG_TLBI_VALE1OS:
case MISCREG_TLBI_ASIDE1IS:
case MISCREG_TLBI_ASIDE1OS:
case MISCREG_TLBI_VAAE1IS:
case MISCREG_TLBI_VAAE1OS:
case MISCREG_TLBI_VAALE1IS:
case MISCREG_TLBI_VAALE1OS:
case MISCREG_TLBI_IPAS2E1IS:
case MISCREG_TLBI_IPAS2E1OS:
case MISCREG_TLBI_IPAS2LE1IS:
case MISCREG_TLBI_IPAS2LE1OS:
case MISCREG_TLBI_RVAE1IS:
case MISCREG_TLBI_RVAE1OS:
case MISCREG_TLBI_RVAAE1IS:
case MISCREG_TLBI_RVAAE1OS:
case MISCREG_TLBI_RVALE1IS:
case MISCREG_TLBI_RVALE1OS:
case MISCREG_TLBI_RVAALE1IS:
case MISCREG_TLBI_RVAALE1OS:
case MISCREG_TLBI_RIPAS2E1IS:
case MISCREG_TLBI_RIPAS2E1OS:
case MISCREG_TLBI_RIPAS2LE1IS:
case MISCREG_TLBI_RIPAS2LE1OS:
case MISCREG_TLBI_RVAE2IS:
case MISCREG_TLBI_RVAE2OS:
case MISCREG_TLBI_RVALE2IS:
case MISCREG_TLBI_RVALE2OS:
case MISCREG_TLBI_RVAE3IS:
case MISCREG_TLBI_RVAE3OS:
case MISCREG_TLBI_RVALE3IS:
case MISCREG_TLBI_RVALE3OS:
return new Tlbi64ShareableHub(
machInst, miscReg, rt, dec.dvmEnabled);
default:

182
src/arch/arm/mmu.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013, 2016-2023 Arm Limited
* Copyright (c) 2010-2013, 2016-2024 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -178,11 +178,9 @@ MMU::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
lookup_data.asn = state.asid;
lookup_data.ignoreAsn = false;
lookup_data.vmid = state.vmid;
lookup_data.hyp = state.isHyp;
lookup_data.secure = state.isSecure;
lookup_data.functional = true;
lookup_data.targetEL = state.aarch64 ? state.aarch64EL : EL1;
lookup_data.inHost = false;
lookup_data.targetRegime = state.currRegime;
lookup_data.mode = BaseMMU::Read;
TlbEntry *e = tlb->multiLookup(lookup_data);
@@ -240,7 +238,7 @@ MMU::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
Addr vaddr_tainted = req->getVaddr();
Addr vaddr = 0;
if (state.aarch64) {
vaddr = purifyTaggedAddr(vaddr_tainted, tc, state.aarch64EL,
vaddr = purifyTaggedAddr(vaddr_tainted, tc, state.exceptionLevel,
static_cast<TCR>(state.ttbcr), mode==Execute, state);
} else {
vaddr = vaddr_tainted;
@@ -480,12 +478,12 @@ MMU::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
// * It is a data cache invalidate (dc ivac) which requires write
// permissions to the VA, or
// * It is executed from EL0
if (req->isCacheClean() && state.aarch64EL != EL0 && !state.isStage2) {
if (req->isCacheClean() && state.exceptionLevel != EL0 && !state.isStage2) {
return NoFault;
}
Addr vaddr_tainted = req->getVaddr();
Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, state.aarch64EL,
Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, state.exceptionLevel,
static_cast<TCR>(state.ttbcr), mode==Execute, state);
Request::Flags flags = req->getFlags();
@@ -582,7 +580,7 @@ std::pair<bool, bool>
MMU::s2PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode,
ThreadContext *tc, CachedState &state, bool r, bool w, bool x)
{
assert(ArmSystem::haveEL(tc, EL2) && state.aarch64EL != EL2);
assert(ArmSystem::haveEL(tc, EL2) && state.exceptionLevel != EL2);
// In stage 2 we use the hypervisor access permission bits.
// The following permissions are described in ARM DDI 0487A.f
@@ -639,8 +637,8 @@ MMU::s1PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode,
return std::make_pair(false, false);
}
ExceptionLevel regime = !is_priv ? EL0 : state.aarch64EL;
if (hasUnprivRegime(regime, state)) {
TranslationRegime regime = !is_priv ? TranslationRegime::EL10 : state.currRegime;
if (hasUnprivRegime(regime)) {
bool pr = false;
bool pw = false;
bool ur = false;
@@ -702,34 +700,23 @@ MMU::s1PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode,
}
bool
MMU::hasUnprivRegime(ExceptionLevel el, bool e2h)
MMU::hasUnprivRegime(TranslationRegime regime)
{
switch (el) {
case EL0:
case EL1:
// EL1&0
switch (regime) {
case TranslationRegime::EL10:
case TranslationRegime::EL20:
return true;
case EL2:
// EL2&0 or EL2
return e2h;
case EL3:
default:
return false;
}
}
bool
MMU::hasUnprivRegime(ExceptionLevel el, CachedState &state)
{
return hasUnprivRegime(el, state.hcr.e2h);
}
bool
MMU::faultPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode,
const bool is_priv, CachedState &state)
{
bool exception = false;
switch (state.aarch64EL) {
switch (state.exceptionLevel) {
case EL0:
break;
case EL1:
@@ -779,7 +766,8 @@ MMU::checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode,
}
Addr
MMU::purifyTaggedAddr(Addr vaddr_tainted, ThreadContext *tc, ExceptionLevel el,
MMU::purifyTaggedAddr(Addr vaddr_tainted, ThreadContext *tc,
ExceptionLevel el,
TCR tcr, bool is_inst, CachedState& state)
{
const bool selbit = bits(vaddr_tainted, 55);
@@ -839,9 +827,7 @@ MMU::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
bool dc = (HaveExt(tc, ArmExtension::FEAT_VHE) &&
state.hcr.e2h == 1 && state.hcr.tge == 1) ? 0: state.hcr.dc;
bool i_cacheability = state.sctlr.i && !state.sctlr.m;
if (state.isStage2 || !dc || state.isSecure ||
(state.isHyp && !(tran_type & S1CTran))) {
if (state.isStage2 || !dc || state.exceptionLevel == EL2) {
temp_te.mtype = is_fetch ? TlbEntry::MemoryType::Normal
: TlbEntry::MemoryType::StronglyOrdered;
temp_te.innerAttrs = i_cacheability? 0x2: 0x0;
@@ -949,7 +935,7 @@ MMU::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
Addr vaddr_tainted = req->getVaddr();
Addr vaddr = 0;
if (state.aarch64) {
vaddr = purifyTaggedAddr(vaddr_tainted, tc, state.aarch64EL,
vaddr = purifyTaggedAddr(vaddr_tainted, tc, state.exceptionLevel,
static_cast<TCR>(state.ttbcr), mode==Execute, state);
} else {
vaddr = vaddr_tainted;
@@ -1205,44 +1191,23 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
ArmTranslationType tran_type)
{
cpsr = tc->readMiscReg(MISCREG_CPSR);
hcr = tc->readMiscReg(MISCREG_HCR_EL2);
scr = tc->readMiscReg(MISCREG_SCR_EL3);
// Dependencies: SCR/SCR_EL3, CPSR
isSecure = ArmISA::isSecure(tc) &&
!(tran_type & HypMode) && !(tran_type & S1S2NsTran);
aarch64EL = tranTypeEL(cpsr, tran_type);
exceptionLevel = tranTypeEL(cpsr, scr, tran_type);
currRegime = translationRegime(tc, exceptionLevel);
aarch64 = isStage2 ?
ELIs64(tc, EL2) :
ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL);
ELIs64(tc, translationEl(currRegime));
hcr = tc->readMiscReg(MISCREG_HCR_EL2);
if (aarch64) { // AArch64
// determine EL we need to translate in
switch (aarch64EL) {
case EL0:
if (HaveExt(tc, ArmExtension::FEAT_VHE) &&
hcr.tge == 1 && hcr.e2h == 1) {
// VHE code for EL2&0 regime
sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
ttbcr = tc->readMiscReg(MISCREG_TCR_EL2);
uint64_t ttbr_asid = ttbcr.a1 ?
tc->readMiscReg(MISCREG_TTBR1_EL2) :
tc->readMiscReg(MISCREG_TTBR0_EL2);
asid = bits(ttbr_asid,
(mmu->haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48);
} else {
sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
ttbcr = tc->readMiscReg(MISCREG_TCR_EL1);
uint64_t ttbr_asid = ttbcr.a1 ?
tc->readMiscReg(MISCREG_TTBR1_EL1) :
tc->readMiscReg(MISCREG_TTBR0_EL1);
asid = bits(ttbr_asid,
(mmu->haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48);
}
break;
case EL1:
switch (currRegime) {
case TranslationRegime::EL10:
{
sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
ttbcr = tc->readMiscReg(MISCREG_TCR_EL1);
@@ -1253,44 +1218,41 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
(mmu->haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48);
}
break;
case EL2:
sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
ttbcr = tc->readMiscReg(MISCREG_TCR_EL2);
if (hcr.e2h == 1) {
case TranslationRegime::EL20:
{
// VHE code for EL2&0 regime
sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
ttbcr = tc->readMiscReg(MISCREG_TCR_EL2);
uint64_t ttbr_asid = ttbcr.a1 ?
tc->readMiscReg(MISCREG_TTBR1_EL2) :
tc->readMiscReg(MISCREG_TTBR0_EL2);
asid = bits(ttbr_asid,
(mmu->haveLargeAsid64 && ttbcr.as) ? 63 : 55, 48);
} else {
asid = -1;
}
break;
case EL3:
case TranslationRegime::EL2:
sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
ttbcr = tc->readMiscReg(MISCREG_TCR_EL2);
asid = -1;
break;
case TranslationRegime::EL3:
sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3);
ttbcr = tc->readMiscReg(MISCREG_TCR_EL3);
asid = -1;
break;
}
scr = tc->readMiscReg(MISCREG_SCR_EL3);
isPriv = aarch64EL != EL0;
isPriv = exceptionLevel != EL0;
if (mmu->release()->has(ArmExtension::VIRTUALIZATION)) {
vmid = getVMID(tc);
isHyp = aarch64EL == EL2;
isHyp |= tran_type & HypMode;
isHyp &= (tran_type & S1S2NsTran) == 0;
isHyp &= (tran_type & S1CTran) == 0;
bool vm = hcr.vm;
if (HaveExt(tc, ArmExtension::FEAT_VHE) &&
hcr.e2h == 1 && hcr.tge ==1) {
vm = 0;
}
if (hcr.e2h == 1 && (aarch64EL == EL2
|| (hcr.tge ==1 && aarch64EL == EL0))) {
isHyp = true;
if (hcr.e2h == 1 && (exceptionLevel == EL2
|| (hcr.tge ==1 && exceptionLevel == EL0))) {
directToStage2 = false;
stage2Req = false;
stage2DescReq = false;
@@ -1298,18 +1260,17 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
// Work out if we should skip the first stage of translation and go
// directly to stage 2. This value is cached so we don't have to
// compute it for every translation.
bool sec = !isSecure || (isSecure && IsSecureEL2Enabled(tc));
const bool el2_enabled = EL2Enabled(tc);
stage2Req = isStage2 ||
(vm && !isHyp && sec &&
!(tran_type & S1CTran) && (aarch64EL < EL2) &&
!(tran_type & S1E1Tran)); // <--- FIX THIS HACK
stage2DescReq = isStage2 || (vm && !isHyp && sec &&
(aarch64EL < EL2));
(vm && exceptionLevel < EL2 && el2_enabled &&
!(tran_type & S1CTran) &&
!(tran_type & S1E1Tran)); // <--- FIX THIS HACK
stage2DescReq = isStage2 ||
(vm && exceptionLevel < EL2 && el2_enabled);
directToStage2 = !isStage2 && stage2Req && !sctlr.m;
}
} else {
vmid = 0;
isHyp = false;
directToStage2 = false;
stage2Req = false;
stage2DescReq = false;
@@ -1319,7 +1280,6 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
!isSecure));
ttbcr = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc,
!isSecure));
scr = tc->readMiscReg(MISCREG_SCR_EL3);
isPriv = cpsr.mode != MODE_USER;
if (longDescFormatInUse(tc)) {
uint64_t ttbr_asid = tc->readMiscReg(
@@ -1338,29 +1298,25 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
!isSecure));
dacr = tc->readMiscReg(snsBankedIndex(MISCREG_DACR, tc,
!isSecure));
hcr = tc->readMiscReg(MISCREG_HCR_EL2);
if (mmu->release()->has(ArmExtension::VIRTUALIZATION)) {
vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48);
isHyp = cpsr.mode == MODE_HYP;
isHyp |= tran_type & HypMode;
isHyp &= (tran_type & S1S2NsTran) == 0;
isHyp &= (tran_type & S1CTran) == 0;
if (isHyp) {
if (exceptionLevel == EL2) {
sctlr = tc->readMiscReg(MISCREG_HSCTLR);
}
// Work out if we should skip the first stage of translation and go
// directly to stage 2. This value is cached so we don't have to
// compute it for every translation.
bool sec = !isSecure || (isSecure && IsSecureEL2Enabled(tc));
stage2Req = hcr.vm && !isStage2 && !isHyp && sec &&
!(tran_type & S1CTran);
stage2DescReq = hcr.vm && !isStage2 && !isHyp && sec;
directToStage2 = stage2Req && !sctlr.m;
const bool el2_enabled = EL2Enabled(tc);
stage2Req = isStage2 ||
(hcr.vm && exceptionLevel < EL2 && el2_enabled &&
!(tran_type & S1CTran));
stage2DescReq = isStage2 ||
(hcr.vm && exceptionLevel < EL2 && el2_enabled);
directToStage2 = !isStage2 && stage2Req && !sctlr.m;
} else {
vmid = 0;
stage2Req = false;
isHyp = false;
directToStage2 = false;
stage2DescReq = false;
}
@@ -1370,7 +1326,7 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
}
ExceptionLevel
MMU::tranTypeEL(CPSR cpsr, ArmTranslationType type)
MMU::tranTypeEL(CPSR cpsr, SCR scr, ArmTranslationType type)
{
switch (type) {
case S1E0Tran:
@@ -1379,18 +1335,21 @@ MMU::tranTypeEL(CPSR cpsr, ArmTranslationType type)
case S1E1Tran:
case S12E1Tran:
case S1S2NsTran:
return EL1;
case S1E2Tran:
case HypMode:
return EL2;
case S1E3Tran:
return EL3;
case NormalTran:
case S1CTran:
case S1S2NsTran:
case HypMode:
return currEL(cpsr) == EL3 && scr.ns == 0 ?
EL3 : EL1;
case NormalTran:
return currEL(cpsr);
default:
@@ -1409,9 +1368,9 @@ MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
}
TlbEntry*
MMU::lookup(Addr va, uint16_t asid, vmid_t vmid, bool hyp, bool secure,
bool functional, bool ignore_asn, ExceptionLevel target_el,
bool in_host, bool stage2, BaseMMU::Mode mode)
MMU::lookup(Addr va, uint16_t asid, vmid_t vmid, bool secure,
bool functional, bool ignore_asn, TranslationRegime regime,
bool stage2, BaseMMU::Mode mode)
{
TLB *tlb = getTlb(mode, stage2);
@@ -1421,11 +1380,9 @@ MMU::lookup(Addr va, uint16_t asid, vmid_t vmid, bool hyp, bool secure,
lookup_data.asn = asid;
lookup_data.ignoreAsn = ignore_asn;
lookup_data.vmid = vmid;
lookup_data.hyp = hyp;
lookup_data.secure = secure;
lookup_data.functional = functional;
lookup_data.targetEL = target_el;
lookup_data.inHost = in_host;
lookup_data.targetRegime = regime;
lookup_data.mode = mode;
return tlb->multiLookup(lookup_data);
@@ -1445,16 +1402,17 @@ MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
Addr vaddr_tainted = req->getVaddr();
Addr vaddr = 0;
ExceptionLevel target_el = state.aarch64 ? state.aarch64EL : EL1;
TranslationRegime regime = state.currRegime;
if (state.aarch64) {
vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el,
vaddr = purifyTaggedAddr(vaddr_tainted, tc, state.exceptionLevel,
static_cast<TCR>(state.ttbcr), mode==Execute, state);
} else {
vaddr = vaddr_tainted;
}
*te = lookup(vaddr, state.asid, state.vmid, state.isHyp, is_secure, false,
false, target_el, false, state.isStage2, mode);
*te = lookup(vaddr, state.asid, state.vmid, is_secure, false,
false, regime, state.isStage2, mode);
if (!isCompleteTranslation(*te)) {
if (req->isPrefetch()) {
@@ -1474,7 +1432,7 @@ MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
Fault fault;
fault = getTableWalker(mode, state.isStage2)->walk(
req, tc, state.asid, state.vmid, state.isHyp, mode,
req, tc, state.asid, state.vmid, mode,
translation, timing, functional, is_secure,
tran_type, state.stage2DescReq, *te);
@@ -1483,8 +1441,8 @@ MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
return fault;
}
*te = lookup(vaddr, state.asid, state.vmid, state.isHyp, is_secure,
true, false, target_el, false, state.isStage2, mode);
*te = lookup(vaddr, state.asid, state.vmid, is_secure,
true, false, regime, state.isStage2, mode);
assert(*te);
}
return NoFault;

26
src/arch/arm/mmu.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013, 2016, 2019-2022 Arm Limited
* Copyright (c) 2010-2013, 2016, 2019-2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -144,12 +144,12 @@ class MMU : public BaseMMU
isStage2 = rhs.isStage2;
cpsr = rhs.cpsr;
aarch64 = rhs.aarch64;
aarch64EL = EL0;
exceptionLevel = rhs.exceptionLevel;
currRegime = rhs.currRegime;
sctlr = rhs.sctlr;
scr = rhs.scr;
isPriv = rhs.isPriv;
isSecure = rhs.isSecure;
isHyp = rhs.isHyp;
ttbcr = rhs.ttbcr;
asid = rhs.asid;
vmid = rhs.vmid;
@@ -179,12 +179,12 @@ class MMU : public BaseMMU
bool isStage2 = false;
CPSR cpsr = 0;
bool aarch64 = false;
ExceptionLevel aarch64EL = EL0;
ExceptionLevel exceptionLevel = EL0;
TranslationRegime currRegime = TranslationRegime::EL10;
SCTLR sctlr = 0;
SCR scr = 0;
bool isPriv = false;
bool isSecure = false;
bool isHyp = false;
TTBCR ttbcr = 0;
uint16_t asid = 0;
vmid_t vmid = 0;
@@ -388,9 +388,9 @@ class MMU : public BaseMMU
* a specific translation type. If the translation type doesn't
* specify an EL, we use the current EL.
*/
static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
static ExceptionLevel tranTypeEL(CPSR cpsr, SCR scr, ArmTranslationType type);
static bool hasUnprivRegime(ExceptionLevel el, bool e2h);
static bool hasUnprivRegime(TranslationRegime regime);
public:
/** Lookup an entry in the TLB
@@ -398,18 +398,16 @@ class MMU : public BaseMMU
* @param asn context id/address space id to use
* @param vmid The virtual machine ID used for stage 2 translation
* @param secure if the lookup is secure
* @param hyp if the lookup is done from hyp mode
* @param functional if the lookup should modify state
* @param ignore_asn if on lookup asn should be ignored
* @param target_el selecting the translation regime
* @param in_host if we are in host (EL2&0 regime)
* @param target_regime selecting the translation regime
* @param mode to differentiate between read/writes/fetches.
* @return pointer to TLB entry if it exists
*/
TlbEntry *lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp,
TlbEntry *lookup(Addr vpn, uint16_t asn, vmid_t vmid,
bool secure, bool functional,
bool ignore_asn, ExceptionLevel target_el,
bool in_host, bool stage2, BaseMMU::Mode mode);
bool ignore_asn, TranslationRegime target_regime,
bool stage2, BaseMMU::Mode mode);
Fault getTE(TlbEntry **te, const RequestPtr &req,
ThreadContext *tc, Mode mode,
@@ -448,8 +446,6 @@ class MMU : public BaseMMU
bool faultPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
Mode mode, const bool is_priv, CachedState &state);
bool hasUnprivRegime(ExceptionLevel el, CachedState &state);
std::pair<bool, bool> s1PermBits64(
TlbEntry *te, const RequestPtr &req, Mode mode,
ThreadContext *tc, CachedState &state, bool r, bool w, bool x);

54
src/arch/arm/pagetable.hh
View File

@@ -198,16 +198,12 @@ struct TlbEntry : public Serializable
bool ignoreAsn = false;
// The virtual machine ID used for stage 2 translation
vmid_t vmid = 0;
// if the lookup is done from hyp mode
bool hyp = false;
// if the lookup is secure
bool secure = false;
// if the lookup should modify state
bool functional = false;
// selecting the translation regime
ExceptionLevel targetEL = EL0;
// if we are in host (EL2&0 regime)
bool inHost = false;
TranslationRegime targetRegime = TranslationRegime::EL10;
// mode to differentiate between read/writes/fetches.
BaseMMU::Mode mode = BaseMMU::Read;
};
@@ -238,7 +234,6 @@ struct TlbEntry : public Serializable
// True if the long descriptor format is used for this entry (LPAE only)
bool longDescFormat; // @todo use this in the update attribute bethod
bool isHyp;
bool global;
bool valid;
@@ -246,8 +241,8 @@ struct TlbEntry : public Serializable
bool ns;
// True if the entry was brought in from a non-secure page table
bool nstid;
// Exception level on insert, AARCH64 EL0&1, AARCH32 -> el=1
ExceptionLevel el;
// Translation regime on insert, AARCH64 EL0&1, AARCH32 -> el=1
TranslationRegime regime;
// This is used to distinguish between instruction and data entries
// in unified TLBs
TypeTLB type;
@@ -273,9 +268,9 @@ struct TlbEntry : public Serializable
asid(_asn), vmid(0), tg(Grain4KB), N(0),
innerAttrs(0), outerAttrs(0), ap(read_only ? 0x3 : 0), hap(0x3),
domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
longDescFormat(false), isHyp(false), global(false), valid(true),
ns(true), nstid(true), el(EL0), type(TypeTLB::unified),
partial(false),
longDescFormat(false), global(false), valid(true),
ns(true), nstid(true), regime(TranslationRegime::EL10),
type(TypeTLB::unified), partial(false),
nonCacheable(uncacheable),
shareable(false), outerShareable(false), xn(0), pxn(0)
{
@@ -291,9 +286,9 @@ struct TlbEntry : public Serializable
asid(0), vmid(0), tg(ReservedGrain), N(0),
innerAttrs(0), outerAttrs(0), ap(0), hap(0x3),
domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
longDescFormat(false), isHyp(false), global(false), valid(false),
ns(true), nstid(true), el(EL0), type(TypeTLB::unified),
partial(false), nonCacheable(false),
longDescFormat(false), global(false), valid(false),
ns(true), nstid(true), regime(TranslationRegime::EL10),
type(TypeTLB::unified), partial(false), nonCacheable(false),
shareable(false), outerShareable(false), xn(0), pxn(0)
{
// no restrictions by default, hap = 0x3
@@ -332,14 +327,14 @@ struct TlbEntry : public Serializable
{
bool match = false;
if (valid && matchAddress(lookup) &&
(lookup.secure == !nstid) && (lookup.hyp == isHyp))
(lookup.secure == !nstid))
{
match = checkELMatch(lookup.targetEL, lookup.inHost);
match = checkRegime(lookup.targetRegime);
if (match && !lookup.ignoreAsn) {
match = global || (lookup.asn == asid);
}
if (match && useVMID(lookup.targetEL, lookup.inHost)) {
if (match && useVMID(lookup.targetRegime)) {
match = lookup.vmid == vmid;
}
}
@@ -347,21 +342,9 @@ struct TlbEntry : public Serializable
}
bool
checkELMatch(ExceptionLevel target_el, bool in_host) const
checkRegime(TranslationRegime target_regime) const
{
switch (target_el) {
case EL3:
return el == EL3;
case EL2:
{
return el == EL2 || (el == EL0 && in_host);
}
case EL1:
case EL0:
return (el == EL0) || (el == EL1);
default:
return false;
}
return regime == target_regime;
}
Addr
@@ -422,9 +405,10 @@ struct TlbEntry : public Serializable
std::string
print() const
{
return csprintf("%#x, asn %d vmn %d hyp %d ppn %#x size: %#x ap:%d "
"ns:%d nstid:%d g:%d el:%d", vpn << N, asid, vmid,
isHyp, pfn << N, size, ap, ns, nstid, global, el);
return csprintf("%#x, asn %d vmn %d ppn %#x size: %#x ap:%d "
"ns:%d nstid:%d g:%d regime:%s", vpn << N, asid, vmid,
pfn << N, size, ap, ns, nstid, global,
regimeToStr(regime));
}
void
@@ -436,7 +420,6 @@ struct TlbEntry : public Serializable
SERIALIZE_SCALAR(vpn);
SERIALIZE_SCALAR(asid);
SERIALIZE_SCALAR(vmid);
SERIALIZE_SCALAR(isHyp);
SERIALIZE_SCALAR(N);
SERIALIZE_SCALAR(global);
SERIALIZE_SCALAR(valid);
@@ -467,7 +450,6 @@ struct TlbEntry : public Serializable
UNSERIALIZE_SCALAR(vpn);
UNSERIALIZE_SCALAR(asid);
UNSERIALIZE_SCALAR(vmid);
UNSERIALIZE_SCALAR(isHyp);
UNSERIALIZE_SCALAR(N);
UNSERIALIZE_SCALAR(global);
UNSERIALIZE_SCALAR(valid);

252
src/arch/arm/regs/misc.cc
View File

@@ -754,35 +754,35 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
{ MiscRegNum64(1, 0, 7, 10, 2), MISCREG_DC_CSW_Xt },
{ MiscRegNum64(1, 0, 7, 14, 2), MISCREG_DC_CISW_Xt },
{ MiscRegNum64(1, 0, 8, 1, 0), MISCREG_TLBI_VMALLE1OS },
{ MiscRegNum64(1, 0, 8, 1, 1), MISCREG_TLBI_VAE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 1, 2), MISCREG_TLBI_ASIDE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 1, 3), MISCREG_TLBI_VAAE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 1, 5), MISCREG_TLBI_VALE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 1, 7), MISCREG_TLBI_VAALE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 2, 1), MISCREG_TLBI_RVAE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 2, 3), MISCREG_TLBI_RVAAE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 2, 5), MISCREG_TLBI_RVALE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 2, 7), MISCREG_TLBI_RVAALE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 1, 1), MISCREG_TLBI_VAE1OS },
{ MiscRegNum64(1, 0, 8, 1, 2), MISCREG_TLBI_ASIDE1OS },
{ MiscRegNum64(1, 0, 8, 1, 3), MISCREG_TLBI_VAAE1OS },
{ MiscRegNum64(1, 0, 8, 1, 5), MISCREG_TLBI_VALE1OS },
{ MiscRegNum64(1, 0, 8, 1, 7), MISCREG_TLBI_VAALE1OS },
{ MiscRegNum64(1, 0, 8, 2, 1), MISCREG_TLBI_RVAE1IS },
{ MiscRegNum64(1, 0, 8, 2, 3), MISCREG_TLBI_RVAAE1IS },
{ MiscRegNum64(1, 0, 8, 2, 5), MISCREG_TLBI_RVALE1IS },
{ MiscRegNum64(1, 0, 8, 2, 7), MISCREG_TLBI_RVAALE1IS },
{ MiscRegNum64(1, 0, 8, 3, 0), MISCREG_TLBI_VMALLE1IS },
{ MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 3, 3), MISCREG_TLBI_VAAE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 3, 5), MISCREG_TLBI_VALE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 3, 7), MISCREG_TLBI_VAALE1IS_Xt },
{ MiscRegNum64(1, 0, 8, 5, 1), MISCREG_TLBI_RVAE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 5, 3), MISCREG_TLBI_RVAAE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 5, 5), MISCREG_TLBI_RVALE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 5, 7), MISCREG_TLBI_RVAALE1OS_Xt },
{ MiscRegNum64(1, 0, 8, 6, 1), MISCREG_TLBI_RVAE1_Xt },
{ MiscRegNum64(1, 0, 8, 6, 3), MISCREG_TLBI_RVAAE1_Xt },
{ MiscRegNum64(1, 0, 8, 6, 5), MISCREG_TLBI_RVALE1_Xt },
{ MiscRegNum64(1, 0, 8, 6, 7), MISCREG_TLBI_RVAALE1_Xt },
{ MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS },
{ MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS },
{ MiscRegNum64(1, 0, 8, 3, 3), MISCREG_TLBI_VAAE1IS },
{ MiscRegNum64(1, 0, 8, 3, 5), MISCREG_TLBI_VALE1IS },
{ MiscRegNum64(1, 0, 8, 3, 7), MISCREG_TLBI_VAALE1IS },
{ MiscRegNum64(1, 0, 8, 5, 1), MISCREG_TLBI_RVAE1OS },
{ MiscRegNum64(1, 0, 8, 5, 3), MISCREG_TLBI_RVAAE1OS },
{ MiscRegNum64(1, 0, 8, 5, 5), MISCREG_TLBI_RVALE1OS },
{ MiscRegNum64(1, 0, 8, 5, 7), MISCREG_TLBI_RVAALE1OS },
{ MiscRegNum64(1, 0, 8, 6, 1), MISCREG_TLBI_RVAE1 },
{ MiscRegNum64(1, 0, 8, 6, 3), MISCREG_TLBI_RVAAE1 },
{ MiscRegNum64(1, 0, 8, 6, 5), MISCREG_TLBI_RVALE1 },
{ MiscRegNum64(1, 0, 8, 6, 7), MISCREG_TLBI_RVAALE1 },
{ MiscRegNum64(1, 0, 8, 7, 0), MISCREG_TLBI_VMALLE1 },
{ MiscRegNum64(1, 0, 8, 7, 1), MISCREG_TLBI_VAE1_Xt },
{ MiscRegNum64(1, 0, 8, 7, 2), MISCREG_TLBI_ASIDE1_Xt },
{ MiscRegNum64(1, 0, 8, 7, 3), MISCREG_TLBI_VAAE1_Xt },
{ MiscRegNum64(1, 0, 8, 7, 5), MISCREG_TLBI_VALE1_Xt },
{ MiscRegNum64(1, 0, 8, 7, 7), MISCREG_TLBI_VAALE1_Xt },
{ MiscRegNum64(1, 0, 8, 7, 1), MISCREG_TLBI_VAE1 },
{ MiscRegNum64(1, 0, 8, 7, 2), MISCREG_TLBI_ASIDE1 },
{ MiscRegNum64(1, 0, 8, 7, 3), MISCREG_TLBI_VAAE1 },
{ MiscRegNum64(1, 0, 8, 7, 5), MISCREG_TLBI_VALE1 },
{ MiscRegNum64(1, 0, 8, 7, 7), MISCREG_TLBI_VAALE1 },
{ MiscRegNum64(1, 3, 7, 4, 1), MISCREG_DC_ZVA_Xt },
{ MiscRegNum64(1, 3, 7, 5, 1), MISCREG_IC_IVAU_Xt },
{ MiscRegNum64(1, 3, 7, 10, 1), MISCREG_DC_CVAC_Xt },
@@ -794,56 +794,56 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
{ MiscRegNum64(1, 4, 7, 8, 5), MISCREG_AT_S12E1W_Xt },
{ MiscRegNum64(1, 4, 7, 8, 6), MISCREG_AT_S12E0R_Xt },
{ MiscRegNum64(1, 4, 7, 8, 7), MISCREG_AT_S12E0W_Xt },
{ MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS_Xt },
{ MiscRegNum64(1, 4, 8, 0, 2), MISCREG_TLBI_RIPAS2E1IS_Xt },
{ MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS_Xt },
{ MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS },
{ MiscRegNum64(1, 4, 8, 0, 2), MISCREG_TLBI_RIPAS2E1IS },
{ MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS },
{ MiscRegNum64(1, 4, 8, 1, 0), MISCREG_TLBI_ALLE2OS },
{ MiscRegNum64(1, 4, 8, 1, 1), MISCREG_TLBI_VAE2OS_Xt },
{ MiscRegNum64(1, 4, 8, 1, 1), MISCREG_TLBI_VAE2OS },
{ MiscRegNum64(1, 4, 8, 1, 4), MISCREG_TLBI_ALLE1OS },
{ MiscRegNum64(1, 4, 8, 1, 5), MISCREG_TLBI_VALE2OS_Xt },
{ MiscRegNum64(1, 4, 8, 1, 5), MISCREG_TLBI_VALE2OS },
{ MiscRegNum64(1, 4, 8, 1, 6), MISCREG_TLBI_VMALLS12E1OS },
{ MiscRegNum64(1, 4, 8, 0, 6), MISCREG_TLBI_RIPAS2LE1IS_Xt },
{ MiscRegNum64(1, 4, 8, 2, 1), MISCREG_TLBI_RVAE2IS_Xt },
{ MiscRegNum64(1, 4, 8, 2, 5), MISCREG_TLBI_RVALE2IS_Xt },
{ MiscRegNum64(1, 4, 8, 0, 6), MISCREG_TLBI_RIPAS2LE1IS },
{ MiscRegNum64(1, 4, 8, 2, 1), MISCREG_TLBI_RVAE2IS },
{ MiscRegNum64(1, 4, 8, 2, 5), MISCREG_TLBI_RVALE2IS },
{ MiscRegNum64(1, 4, 8, 3, 0), MISCREG_TLBI_ALLE2IS },
{ MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS_Xt },
{ MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS },
{ MiscRegNum64(1, 4, 8, 3, 4), MISCREG_TLBI_ALLE1IS },
{ MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS_Xt },
{ MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS },
{ MiscRegNum64(1, 4, 8, 3, 6), MISCREG_TLBI_VMALLS12E1IS },
{ MiscRegNum64(1, 4, 8, 4, 0), MISCREG_TLBI_IPAS2E1OS_Xt },
{ MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1_Xt },
{ MiscRegNum64(1, 4, 8, 4, 2), MISCREG_TLBI_RIPAS2E1_Xt },
{ MiscRegNum64(1, 4, 8, 4, 3), MISCREG_TLBI_RIPAS2E1OS_Xt },
{ MiscRegNum64(1, 4, 8, 4, 4), MISCREG_TLBI_IPAS2LE1OS_Xt },
{ MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1_Xt },
{ MiscRegNum64(1, 4, 8, 4, 6), MISCREG_TLBI_RIPAS2LE1_Xt },
{ MiscRegNum64(1, 4, 8, 4, 7), MISCREG_TLBI_RIPAS2LE1OS_Xt },
{ MiscRegNum64(1, 4, 8, 5, 1), MISCREG_TLBI_RVAE2OS_Xt },
{ MiscRegNum64(1, 4, 8, 5, 5), MISCREG_TLBI_RVALE2OS_Xt },
{ MiscRegNum64(1, 4, 8, 6, 1), MISCREG_TLBI_RVAE2_Xt },
{ MiscRegNum64(1, 4, 8, 6, 5), MISCREG_TLBI_RVALE2_Xt },
{ MiscRegNum64(1, 4, 8, 4, 0), MISCREG_TLBI_IPAS2E1OS },
{ MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1 },
{ MiscRegNum64(1, 4, 8, 4, 2), MISCREG_TLBI_RIPAS2E1 },
{ MiscRegNum64(1, 4, 8, 4, 3), MISCREG_TLBI_RIPAS2E1OS },
{ MiscRegNum64(1, 4, 8, 4, 4), MISCREG_TLBI_IPAS2LE1OS },
{ MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1 },
{ MiscRegNum64(1, 4, 8, 4, 6), MISCREG_TLBI_RIPAS2LE1 },
{ MiscRegNum64(1, 4, 8, 4, 7), MISCREG_TLBI_RIPAS2LE1OS },
{ MiscRegNum64(1, 4, 8, 5, 1), MISCREG_TLBI_RVAE2OS },
{ MiscRegNum64(1, 4, 8, 5, 5), MISCREG_TLBI_RVALE2OS },
{ MiscRegNum64(1, 4, 8, 6, 1), MISCREG_TLBI_RVAE2 },
{ MiscRegNum64(1, 4, 8, 6, 5), MISCREG_TLBI_RVALE2 },
{ MiscRegNum64(1, 4, 8, 7, 0), MISCREG_TLBI_ALLE2 },
{ MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2_Xt },
{ MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2 },
{ MiscRegNum64(1, 4, 8, 7, 4), MISCREG_TLBI_ALLE1 },
{ MiscRegNum64(1, 4, 8, 7, 5), MISCREG_TLBI_VALE2_Xt },
{ MiscRegNum64(1, 4, 8, 7, 5), MISCREG_TLBI_VALE2 },
{ MiscRegNum64(1, 4, 8, 7, 6), MISCREG_TLBI_VMALLS12E1 },
{ MiscRegNum64(1, 6, 7, 8, 0), MISCREG_AT_S1E3R_Xt },
{ MiscRegNum64(1, 6, 7, 8, 1), MISCREG_AT_S1E3W_Xt },
{ MiscRegNum64(1, 6, 8, 1, 0), MISCREG_TLBI_ALLE3OS },
{ MiscRegNum64(1, 6, 8, 1, 1), MISCREG_TLBI_VAE3OS_Xt },
{ MiscRegNum64(1, 6, 8, 1, 5), MISCREG_TLBI_VALE3OS_Xt },
{ MiscRegNum64(1, 6, 8, 2, 1), MISCREG_TLBI_RVAE3IS_Xt },
{ MiscRegNum64(1, 6, 8, 2, 5), MISCREG_TLBI_RVALE3IS_Xt },
{ MiscRegNum64(1, 6, 8, 1, 1), MISCREG_TLBI_VAE3OS },
{ MiscRegNum64(1, 6, 8, 1, 5), MISCREG_TLBI_VALE3OS },
{ MiscRegNum64(1, 6, 8, 2, 1), MISCREG_TLBI_RVAE3IS },
{ MiscRegNum64(1, 6, 8, 2, 5), MISCREG_TLBI_RVALE3IS },
{ MiscRegNum64(1, 6, 8, 3, 0), MISCREG_TLBI_ALLE3IS },
{ MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS_Xt },
{ MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS_Xt },
{ MiscRegNum64(1, 6, 8, 5, 1), MISCREG_TLBI_RVAE3OS_Xt },
{ MiscRegNum64(1, 6, 8, 5, 5), MISCREG_TLBI_RVALE3OS_Xt },
{ MiscRegNum64(1, 6, 8, 6, 1), MISCREG_TLBI_RVAE3_Xt },
{ MiscRegNum64(1, 6, 8, 6, 5), MISCREG_TLBI_RVALE3_Xt },
{ MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS },
{ MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS },
{ MiscRegNum64(1, 6, 8, 5, 1), MISCREG_TLBI_RVAE3OS },
{ MiscRegNum64(1, 6, 8, 5, 5), MISCREG_TLBI_RVALE3OS },
{ MiscRegNum64(1, 6, 8, 6, 1), MISCREG_TLBI_RVAE3 },
{ MiscRegNum64(1, 6, 8, 6, 5), MISCREG_TLBI_RVALE3 },
{ MiscRegNum64(1, 6, 8, 7, 0), MISCREG_TLBI_ALLE3 },
{ MiscRegNum64(1, 6, 8, 7, 1), MISCREG_TLBI_VAE3_Xt },
{ MiscRegNum64(1, 6, 8, 7, 5), MISCREG_TLBI_VALE3_Xt },
{ MiscRegNum64(1, 6, 8, 7, 1), MISCREG_TLBI_VAE3 },
{ MiscRegNum64(1, 6, 8, 7, 5), MISCREG_TLBI_VALE3 },
{ MiscRegNum64(2, 0, 0, 0, 2), MISCREG_OSDTRRX_EL1 },
{ MiscRegNum64(2, 0, 0, 0, 4), MISCREG_DBGBVR0_EL1 },
{ MiscRegNum64(2, 0, 0, 0, 5), MISCREG_DBGBCR0_EL1 },
@@ -4998,189 +4998,189 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TLBI_VMALLE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivmalle1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAE1OS_Xt)
InitReg(MISCREG_TLBI_VAE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivae1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_ASIDE1OS_Xt)
InitReg(MISCREG_TLBI_ASIDE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbiaside1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAAE1OS_Xt)
InitReg(MISCREG_TLBI_VAAE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivaae1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VALE1OS_Xt)
InitReg(MISCREG_TLBI_VALE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivale1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAALE1OS_Xt)
InitReg(MISCREG_TLBI_VAALE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivaale1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VMALLE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivmalle1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAE1IS_Xt)
InitReg(MISCREG_TLBI_VAE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivae1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_ASIDE1IS_Xt)
InitReg(MISCREG_TLBI_ASIDE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbiaside1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAAE1IS_Xt)
InitReg(MISCREG_TLBI_VAAE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivaae1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VALE1IS_Xt)
InitReg(MISCREG_TLBI_VALE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivale1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAALE1IS_Xt)
InitReg(MISCREG_TLBI_VAALE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivaale1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VMALLE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivmalle1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAE1_Xt)
InitReg(MISCREG_TLBI_VAE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivae1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_ASIDE1_Xt)
InitReg(MISCREG_TLBI_ASIDE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbiaside1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAAE1_Xt)
InitReg(MISCREG_TLBI_VAAE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivaae1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VALE1_Xt)
InitReg(MISCREG_TLBI_VALE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivale1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_VAALE1_Xt)
InitReg(MISCREG_TLBI_VAALE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivaale1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_IPAS2E1OS_Xt)
InitReg(MISCREG_TLBI_IPAS2E1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2LE1OS_Xt)
InitReg(MISCREG_TLBI_IPAS2LE1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE2OS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2OS_Xt)
InitReg(MISCREG_TLBI_VAE2OS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE2OS_Xt)
InitReg(MISCREG_TLBI_VALE2OS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2E1IS_Xt)
InitReg(MISCREG_TLBI_IPAS2E1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2LE1IS_Xt)
InitReg(MISCREG_TLBI_IPAS2LE1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE2IS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2IS_Xt)
InitReg(MISCREG_TLBI_VAE2IS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE2IS_Xt)
InitReg(MISCREG_TLBI_VALE2IS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2E1_Xt)
InitReg(MISCREG_TLBI_IPAS2E1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2LE1_Xt)
InitReg(MISCREG_TLBI_IPAS2LE1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE2)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2_Xt)
InitReg(MISCREG_TLBI_VAE2)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE2_Xt)
InitReg(MISCREG_TLBI_VALE2)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE3OS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VAE3OS_Xt)
InitReg(MISCREG_TLBI_VAE3OS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE3OS_Xt)
InitReg(MISCREG_TLBI_VALE3OS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE3IS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VAE3IS_Xt)
InitReg(MISCREG_TLBI_VAE3IS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE3IS_Xt)
InitReg(MISCREG_TLBI_VALE3IS)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE3)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VAE3_Xt)
InitReg(MISCREG_TLBI_VAE3)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE3_Xt)
InitReg(MISCREG_TLBI_VALE3)
.monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_RVAE1_Xt)
InitReg(MISCREG_TLBI_RVAE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvae1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAAE1_Xt)
InitReg(MISCREG_TLBI_RVAAE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvaae1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVALE1_Xt)
InitReg(MISCREG_TLBI_RVALE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvale1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAALE1_Xt)
InitReg(MISCREG_TLBI_RVAALE1)
.faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvaale1>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RIPAS2E1_Xt)
InitReg(MISCREG_TLBI_RIPAS2E1)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RIPAS2LE1_Xt)
InitReg(MISCREG_TLBI_RIPAS2LE1)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE2_Xt)
InitReg(MISCREG_TLBI_RVAE2)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVALE2_Xt)
InitReg(MISCREG_TLBI_RVALE2)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE3_Xt)
InitReg(MISCREG_TLBI_RVAE3)
.monWrite();
InitReg(MISCREG_TLBI_RVALE3_Xt)
InitReg(MISCREG_TLBI_RVALE3)
.monWrite();
InitReg(MISCREG_TLBI_RVAE1IS_Xt)
InitReg(MISCREG_TLBI_RVAE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvae1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAAE1IS_Xt)
InitReg(MISCREG_TLBI_RVAAE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvaae1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVALE1IS_Xt)
InitReg(MISCREG_TLBI_RVALE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvale1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAALE1IS_Xt)
InitReg(MISCREG_TLBI_RVAALE1IS)
.faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvaale1is>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RIPAS2E1IS_Xt)
InitReg(MISCREG_TLBI_RIPAS2E1IS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RIPAS2LE1IS_Xt)
InitReg(MISCREG_TLBI_RIPAS2LE1IS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE2IS_Xt)
InitReg(MISCREG_TLBI_RVAE2IS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVALE2IS_Xt)
InitReg(MISCREG_TLBI_RVALE2IS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE3IS_Xt)
InitReg(MISCREG_TLBI_RVAE3IS)
.monWrite();
InitReg(MISCREG_TLBI_RVALE3IS_Xt)
InitReg(MISCREG_TLBI_RVALE3IS)
.monWrite();
InitReg(MISCREG_TLBI_RVAE1OS_Xt)
InitReg(MISCREG_TLBI_RVAE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvae1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAAE1OS_Xt)
InitReg(MISCREG_TLBI_RVAAE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvaae1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVALE1OS_Xt)
InitReg(MISCREG_TLBI_RVALE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvale1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RVAALE1OS_Xt)
InitReg(MISCREG_TLBI_RVAALE1OS)
.faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvaale1os>)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBI_RIPAS2E1OS_Xt)
InitReg(MISCREG_TLBI_RIPAS2E1OS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RIPAS2LE1OS_Xt)
InitReg(MISCREG_TLBI_RIPAS2LE1OS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE2OS_Xt)
InitReg(MISCREG_TLBI_RVAE2OS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVALE2OS_Xt)
InitReg(MISCREG_TLBI_RVALE2OS)
.hypWrite().monWrite();
InitReg(MISCREG_TLBI_RVAE3OS_Xt)
InitReg(MISCREG_TLBI_RVAE3OS)
.monWrite();
InitReg(MISCREG_TLBI_RVALE3OS_Xt)
InitReg(MISCREG_TLBI_RVALE3OS)
.monWrite();
InitReg(MISCREG_PMINTENSET_EL1)
.allPrivileges().exceptUserMode()

252
src/arch/arm/regs/misc.hh
View File

@@ -691,82 +691,82 @@ namespace ArmISA
MISCREG_AT_S1E3W_Xt,
MISCREG_TLBI_VMALLE1IS,
MISCREG_TLBI_VMALLE1OS,
MISCREG_TLBI_VAE1IS_Xt,
MISCREG_TLBI_VAE1OS_Xt,
MISCREG_TLBI_ASIDE1IS_Xt,
MISCREG_TLBI_ASIDE1OS_Xt,
MISCREG_TLBI_VAAE1IS_Xt,
MISCREG_TLBI_VAAE1OS_Xt,
MISCREG_TLBI_VALE1IS_Xt,
MISCREG_TLBI_VALE1OS_Xt,
MISCREG_TLBI_VAALE1IS_Xt,
MISCREG_TLBI_VAALE1OS_Xt,
MISCREG_TLBI_VAE1IS,
MISCREG_TLBI_VAE1OS,
MISCREG_TLBI_ASIDE1IS,
MISCREG_TLBI_ASIDE1OS,
MISCREG_TLBI_VAAE1IS,
MISCREG_TLBI_VAAE1OS,
MISCREG_TLBI_VALE1IS,
MISCREG_TLBI_VALE1OS,
MISCREG_TLBI_VAALE1IS,
MISCREG_TLBI_VAALE1OS,
MISCREG_TLBI_VMALLE1,
MISCREG_TLBI_VAE1_Xt,
MISCREG_TLBI_ASIDE1_Xt,
MISCREG_TLBI_VAAE1_Xt,
MISCREG_TLBI_VALE1_Xt,
MISCREG_TLBI_VAALE1_Xt,
MISCREG_TLBI_IPAS2E1IS_Xt,
MISCREG_TLBI_IPAS2E1OS_Xt,
MISCREG_TLBI_IPAS2LE1IS_Xt,
MISCREG_TLBI_IPAS2LE1OS_Xt,
MISCREG_TLBI_VAE1,
MISCREG_TLBI_ASIDE1,
MISCREG_TLBI_VAAE1,
MISCREG_TLBI_VALE1,
MISCREG_TLBI_VAALE1,
MISCREG_TLBI_IPAS2E1IS,
MISCREG_TLBI_IPAS2E1OS,
MISCREG_TLBI_IPAS2LE1IS,
MISCREG_TLBI_IPAS2LE1OS,
MISCREG_TLBI_ALLE2IS,
MISCREG_TLBI_ALLE2OS,
MISCREG_TLBI_VAE2IS_Xt,
MISCREG_TLBI_VAE2OS_Xt,
MISCREG_TLBI_VAE2IS,
MISCREG_TLBI_VAE2OS,
MISCREG_TLBI_ALLE1IS,
MISCREG_TLBI_ALLE1OS,
MISCREG_TLBI_VALE2IS_Xt,
MISCREG_TLBI_VALE2OS_Xt,
MISCREG_TLBI_VALE2IS,
MISCREG_TLBI_VALE2OS,
MISCREG_TLBI_VMALLS12E1IS,
MISCREG_TLBI_VMALLS12E1OS,
MISCREG_TLBI_IPAS2E1_Xt,
MISCREG_TLBI_IPAS2LE1_Xt,
MISCREG_TLBI_IPAS2E1,
MISCREG_TLBI_IPAS2LE1,
MISCREG_TLBI_ALLE2,
MISCREG_TLBI_VAE2_Xt,
MISCREG_TLBI_VAE2,
MISCREG_TLBI_ALLE1,
MISCREG_TLBI_VALE2_Xt,
MISCREG_TLBI_VALE2,
MISCREG_TLBI_VMALLS12E1,
MISCREG_TLBI_ALLE3IS,
MISCREG_TLBI_ALLE3OS,
MISCREG_TLBI_VAE3IS_Xt,
MISCREG_TLBI_VAE3OS_Xt,
MISCREG_TLBI_VALE3IS_Xt,
MISCREG_TLBI_VALE3OS_Xt,
MISCREG_TLBI_VAE3IS,
MISCREG_TLBI_VAE3OS,
MISCREG_TLBI_VALE3IS,
MISCREG_TLBI_VALE3OS,
MISCREG_TLBI_ALLE3,
MISCREG_TLBI_VAE3_Xt,
MISCREG_TLBI_VALE3_Xt,
MISCREG_TLBI_RVAE1_Xt,
MISCREG_TLBI_RVAAE1_Xt,
MISCREG_TLBI_RVALE1_Xt,
MISCREG_TLBI_RVAALE1_Xt,
MISCREG_TLBI_RIPAS2E1_Xt,
MISCREG_TLBI_RIPAS2LE1_Xt,
MISCREG_TLBI_RVAE2_Xt,
MISCREG_TLBI_RVALE2_Xt,
MISCREG_TLBI_RVAE3_Xt,
MISCREG_TLBI_RVALE3_Xt,
MISCREG_TLBI_RVAE1IS_Xt,
MISCREG_TLBI_RVAAE1IS_Xt,
MISCREG_TLBI_RVALE1IS_Xt,
MISCREG_TLBI_RVAALE1IS_Xt,
MISCREG_TLBI_RIPAS2E1IS_Xt,
MISCREG_TLBI_RIPAS2LE1IS_Xt,
MISCREG_TLBI_RVAE2IS_Xt,
MISCREG_TLBI_RVALE2IS_Xt,
MISCREG_TLBI_RVAE3IS_Xt,
MISCREG_TLBI_RVALE3IS_Xt,
MISCREG_TLBI_RVAE1OS_Xt,
MISCREG_TLBI_RVAAE1OS_Xt,
MISCREG_TLBI_RVALE1OS_Xt,
MISCREG_TLBI_RVAALE1OS_Xt,
MISCREG_TLBI_RIPAS2E1OS_Xt,
MISCREG_TLBI_RIPAS2LE1OS_Xt,
MISCREG_TLBI_RVAE2OS_Xt,
MISCREG_TLBI_RVALE2OS_Xt,
MISCREG_TLBI_RVAE3OS_Xt,
MISCREG_TLBI_RVALE3OS_Xt,
MISCREG_TLBI_VAE3,
MISCREG_TLBI_VALE3,
MISCREG_TLBI_RVAE1,
MISCREG_TLBI_RVAAE1,
MISCREG_TLBI_RVALE1,
MISCREG_TLBI_RVAALE1,
MISCREG_TLBI_RIPAS2E1,
MISCREG_TLBI_RIPAS2LE1,
MISCREG_TLBI_RVAE2,
MISCREG_TLBI_RVALE2,
MISCREG_TLBI_RVAE3,
MISCREG_TLBI_RVALE3,
MISCREG_TLBI_RVAE1IS,
MISCREG_TLBI_RVAAE1IS,
MISCREG_TLBI_RVALE1IS,
MISCREG_TLBI_RVAALE1IS,
MISCREG_TLBI_RIPAS2E1IS,
MISCREG_TLBI_RIPAS2LE1IS,
MISCREG_TLBI_RVAE2IS,
MISCREG_TLBI_RVALE2IS,
MISCREG_TLBI_RVAE3IS,
MISCREG_TLBI_RVALE3IS,
MISCREG_TLBI_RVAE1OS,
MISCREG_TLBI_RVAAE1OS,
MISCREG_TLBI_RVALE1OS,
MISCREG_TLBI_RVAALE1OS,
MISCREG_TLBI_RIPAS2E1OS,
MISCREG_TLBI_RIPAS2LE1OS,
MISCREG_TLBI_RVAE2OS,
MISCREG_TLBI_RVALE2OS,
MISCREG_TLBI_RVAE3OS,
MISCREG_TLBI_RVALE3OS,
MISCREG_PMINTENSET_EL1,
MISCREG_PMINTENCLR_EL1,
MISCREG_PMCR_EL0,
@@ -2418,82 +2418,82 @@ namespace ArmISA
"at_s1e3w_xt",
"tlbi_vmalle1is",
"tlbi_vmalle1os",
"tlbi_vae1is_xt",
"tlbi_vae1os_xt",
"tlbi_aside1is_xt",
"tlbi_aside1os_xt",
"tlbi_vaae1is_xt",
"tlbi_vaae1os_xt",
"tlbi_vale1is_xt",
"tlbi_vale1os_xt",
"tlbi_vaale1is_xt",
"tlbi_vaale1os_xt",
"tlbi_vae1is",
"tlbi_vae1os",
"lbi_aside1is_xt",
"tlbi_aside1os",
"tlbi_vaae1is",
"tlbi_vaae1os",
"tlbi_vale1is",
"tlbi_vale1os",
"tlbi_vaale1is",
"tlbi_vaale1os",
"tlbi_vmalle1",
"tlbi_vae1_xt",
"tlbi_aside1_xt",
"tlbi_vaae1_xt",
"tlbi_vale1_xt",
"tlbi_vaale1_xt",
"tlbi_ipas2e1is_xt",
"tlbi_ipas2e1os_xt",
"tlbi_ipas2le1is_xt",
"tlbi_ipas2le1os_xt",
"tlbi_vae1",
"tlbi_aside1",
"tlbi_vaae1",
"tlbi_vale1",
"tlbi_vaale1",
"tlbi_ipas2e1is",
"tlbi_ipas2e1os",
"tlbi_ipas2le1is",
"tlbi_ipas2le1os",
"tlbi_alle2is",
"tlbi_alle2os",
"tlbi_vae2is_xt",
"tlbi_vae2os_xt",
"tlbi_vae2is",
"tlbi_vae2os",
"tlbi_alle1is",
"tlbi_alle1os",
"tlbi_vale2is_xt",
"tlbi_vale2os_xt",
"tlbi_vale2is",
"tlbi_vale2os",
"tlbi_vmalls12e1is",
"tlbi_vmalls12e1os",
"tlbi_ipas2e1_xt",
"tlbi_ipas2le1_xt",
"tlbi_ipas2e1",
"tlbi_ipas2le1",
"tlbi_alle2",
"tlbi_vae2_xt",
"tlbi_vae2",
"tlbi_alle1",
"tlbi_vale2_xt",
"tlbi_vale2",
"tlbi_vmalls12e1",
"tlbi_alle3is",
"tlbi_alle3os",
"tlbi_vae3is_xt",
"tlbi_vae3os_xt",
"tlbi_vale3is_xt",
"tlbi_vale3os_xt",
"tlbi_vae3is",
"tlbi_vae3os",
"tlbi_vale3is",
"tlbi_vale3os",
"tlbi_alle3",
"tlbi_vae3_xt",
"tlbi_vale3_xt",
"tlbi_rvae1_xt",
"tlbi_rvaae1_xt",
"tlbi_rvale1_xt",
"tlbi_rvaale1_xt",
"tlbi_ripas2e1_xt",
"tlbi_ripas2le1_xt",
"tlbi_rvae2_xt",
"tlbi_rvale2_xt",
"tlbi_rvae3_xt",
"tlbi_rvale3_xt",
"tlbi_rvae1is_xt",
"tlbi_rvaae1is_xt",
"tlbi_rvale1is_xt",
"tlbi_rvaale1is_xt",
"tlbi_ripas2e1is_xt",
"tlbi_ripas2le1is_xt",
"tlbi_rvae2is_xt",
"tlbi_rvale2is_xt",
"tlbi_rvae3is_xt",
"tlbi_rvale3is_xt",
"tlbi_rvae1os_xt",
"tlbi_rvaae1os_xt",
"tlbi_rvale1os_xt",
"tlbi_rvaale1os_xt",
"tlbi_ripas2e1os_xt",
"tlbi_ripas2le1os_xt",
"tlbi_rvae2os_xt",
"tlbi_rvale2os_xt",
"tlbi_rvae3os_xt",
"tlbi_rvale3os_xt",
"tlbi_vae3",
"tlbi_vale3",
"tlbi_rvae1",
"tlbi_rvaae1",
"tlbi_rvale1",
"tlbi_rvaale1",
"tlbi_ripas2e1",
"tlbi_ripas2le1",
"tlbi_rvae2",
"tlbi_rvale2",
"tlbi_rvae3",
"tlbi_rvale3",
"tlbi_rvae1is",
"tlbi_rvaae1is",
"tlbi_rvale1is",
"tlbi_rvaale1is",
"tlbi_ripas2e1is",
"tlbi_ripas2le1is",
"tlbi_rvae2is",
"tlbi_rvale2is",
"tlbi_rvae3is",
"tlbi_rvale3is",
"tlbi_rvae1os",
"tlbi_rvaae1os",
"tlbi_rvale1os",
"tlbi_rvaale1os",
"tlbi_ripas2e1os",
"tlbi_ripas2le1os",
"tlbi_rvae2os",
"tlbi_rvale2os",
"tlbi_rvae3os",
"tlbi_rvale3os",
"pmintenset_el1",
"pmintenclr_el1",
"pmcr_el0",

148
src/arch/arm/table_walker.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2019, 2021-2023 Arm Limited
* Copyright (c) 2010, 2012-2019, 2021-2024 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -123,8 +123,9 @@ TableWalker::setMmu(MMU *_mmu)
}
TableWalker::WalkerState::WalkerState() :
tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr),
asid(0), vmid(0), isHyp(false), transState(nullptr),
tc(nullptr), aarch64(false), regime(TranslationRegime::EL10),
physAddrRange(0), req(nullptr),
asid(0), vmid(0), transState(nullptr),
vaddr(0), vaddr_tainted(0),
sctlr(0), scr(0), cpsr(0), tcr(0),
htcr(0), hcr(0), vtcr(0),
@@ -288,7 +289,7 @@ TableWalker::drainResume()
Fault
TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid,
vmid_t _vmid, bool _isHyp, MMU::Mode _mode,
vmid_t _vmid, MMU::Mode _mode,
MMU::Translation *_trans, bool _timing, bool _functional,
bool secure, MMU::ArmTranslationType tranType,
bool _stage2Req, const TlbEntry *walk_entry)
@@ -336,12 +337,17 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid,
// even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64.
if (isStage2) {
currState->el = EL1;
currState->regime = TranslationRegime::EL10;
currState->aarch64 = ELIs64(_tc, EL2);
} else {
currState->el =
MMU::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType);
MMU::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR),
_tc->readMiscReg(MISCREG_SCR_EL3),
tranType);
currState->regime =
translationRegime(_tc, currState->el);
currState->aarch64 =
ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el);
ELIs64(_tc, translationEl(currState->regime));
}
currState->transState = _trans;
currState->req = _req;
@@ -353,7 +359,6 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid,
currState->fault = NoFault;
currState->asid = _asid;
currState->vmid = _vmid;
currState->isHyp = _isHyp;
currState->timing = _timing;
currState->functional = _functional;
currState->mode = _mode;
@@ -382,33 +387,24 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid,
currState->vtcr =
currState->tc->readMiscReg(MISCREG_VTCR_EL2);
}
} else switch (currState->el) {
case EL0:
if (HaveExt(currState->tc, ArmExtension::FEAT_VHE) &&
currState->hcr.tge == 1 && currState->hcr.e2h ==1) {
currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
} else {
currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
}
break;
case EL1:
} else switch (currState->regime) {
case TranslationRegime::EL10:
currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
break;
case EL2:
case TranslationRegime::EL20:
case TranslationRegime::EL2:
assert(release->has(ArmExtension::VIRTUALIZATION));
currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
break;
case EL3:
case TranslationRegime::EL3:
assert(release->has(ArmExtension::SECURITY));
currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3);
break;
default:
panic("Invalid exception level");
panic("Invalid translation regime");
break;
}
} else {
@@ -429,7 +425,8 @@ TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid,
currState->stage2Req = _stage2Req && !isStage2;
bool long_desc_format = currState->aarch64 || _isHyp || isStage2 ||
bool hyp = currState->el == EL2;
bool long_desc_format = currState->aarch64 || hyp || isStage2 ||
longDescFormatInUse(currState->tc);
if (long_desc_format) {
@@ -492,8 +489,8 @@ TableWalker::processWalkWrapper()
// Check if a previous walk filled this request already
// @TODO Should this always be the TLB or should we look in the stage2 TLB?
TlbEntry* te = mmu->lookup(currState->vaddr, currState->asid,
currState->vmid, currState->isHyp, currState->isSecure, true, false,
currState->el, false, isStage2, currState->mode);
currState->vmid, currState->isSecure, true, false,
currState->regime, isStage2, currState->mode);
// Check if we still need to have a walk for this request. If the requesting
// instruction has been squashed, or a previous walk has filled the TLB with
@@ -513,8 +510,9 @@ TableWalker::processWalkWrapper()
Fault f;
if (currState->aarch64)
f = processWalkAArch64();
else if (longDescFormatInUse(currState->tc) ||
currState->isHyp || isStage2)
else if (bool hyp = currState->el == EL2;
longDescFormatInUse(currState->tc) ||
hyp || isStage2)
f = processWalkLPAE();
else
f = processWalk();
@@ -563,8 +561,8 @@ TableWalker::processWalkWrapper()
if (pendingQueue.size()) {
currState = pendingQueue.front();
te = mmu->lookup(currState->vaddr, currState->asid,
currState->vmid, currState->isHyp, currState->isSecure, true,
false, currState->el, false, isStage2, currState->mode);
currState->vmid, currState->isSecure, true,
false, currState->regime, isStage2, currState->mode);
} else {
// Terminate the loop, nothing more to do
currState = NULL;
@@ -713,7 +711,7 @@ TableWalker::processWalkLPAE()
start_lookup_level = currState->vtcr.sl0 ?
LookupLevel::L1 : LookupLevel::L2;
currState->isUncacheable = currState->vtcr.irgn0 == 0;
} else if (currState->isHyp) {
} else if (currState->el == EL2) {
DPRINTF(TLB, " - Selecting HTTBR (long-desc.)\n");
ttbr = currState->tc->readMiscReg(MISCREG_HTTBR);
tsz = currState->htcr.t0sz;
@@ -910,55 +908,8 @@ TableWalker::processWalkAArch64()
currState->el);
bool vaddr_fault = false;
switch (currState->el) {
case EL0:
{
Addr ttbr0;
Addr ttbr1;
if (HaveExt(currState->tc, ArmExtension::FEAT_VHE) &&
currState->hcr.tge==1 && currState->hcr.e2h == 1) {
// VHE code for EL2&0 regime
ttbr0 = currState->tc->readMiscReg(MISCREG_TTBR0_EL2);
ttbr1 = currState->tc->readMiscReg(MISCREG_TTBR1_EL2);
} else {
ttbr0 = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
ttbr1 = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
}
switch (bits(currState->vaddr, 63,48)) {
case 0:
DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
ttbr = ttbr0;
tsz = 64 - currState->tcr.t0sz;
tg = GrainMap_tg0[currState->tcr.tg0];
currState->hpd = currState->tcr.hpd0;
currState->isUncacheable = currState->tcr.irgn0 == 0;
vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
top_bit, tg, tsz, true);
if (vaddr_fault || currState->tcr.epd0)
fault = true;
break;
case 0xffff:
DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
ttbr = ttbr1;
tsz = 64 - currState->tcr.t1sz;
tg = GrainMap_tg1[currState->tcr.tg1];
currState->hpd = currState->tcr.hpd1;
currState->isUncacheable = currState->tcr.irgn1 == 0;
vaddr_fault = checkVAddrSizeFaultAArch64(currState->vaddr,
top_bit, tg, tsz, false);
if (vaddr_fault || currState->tcr.epd1)
fault = true;
break;
default:
// top two bytes must be all 0s or all 1s, else invalid addr
fault = true;
}
ps = currState->tcr.ips;
}
break;
case EL1:
switch (currState->regime) {
case TranslationRegime::EL10:
if (isStage2) {
if (currState->secureLookup) {
DPRINTF(TLB, " - Selecting VSTTBR_EL2 (AArch64 stage 2)\n");
@@ -1007,7 +958,8 @@ TableWalker::processWalkAArch64()
ps = currState->tcr.ips;
}
break;
case EL2:
case TranslationRegime::EL2:
case TranslationRegime::EL20:
switch(bits(currState->vaddr, top_bit)) {
case 0:
DPRINTF(TLB, " - Selecting TTBR0_EL2 (AArch64)\n");
@@ -1044,7 +996,7 @@ TableWalker::processWalkAArch64()
}
ps = currState->hcr.e2h ? currState->tcr.ips: currState->tcr.ps;
break;
case EL3:
case TranslationRegime::EL3:
switch(bits(currState->vaddr, top_bit)) {
case 0:
DPRINTF(TLB, " - Selecting TTBR0_EL3 (AArch64)\n");
@@ -1608,19 +1560,18 @@ TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
uint8_t attrIndx = l_descriptor.attrIndx();
DPRINTF(TLBVerbose, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx, sh);
ExceptionLevel regime = s1TranslationRegime(tc, currState->el);
// Select MAIR
uint64_t mair;
switch (regime) {
case EL0:
case EL1:
switch (currState->regime) {
case TranslationRegime::EL10:
mair = tc->readMiscReg(MISCREG_MAIR_EL1);
break;
case EL2:
case TranslationRegime::EL20:
case TranslationRegime::EL2:
mair = tc->readMiscReg(MISCREG_MAIR_EL2);
break;
case EL3:
case TranslationRegime::EL3:
mair = tc->readMiscReg(MISCREG_MAIR_EL3);
break;
default:
@@ -2299,9 +2250,7 @@ TableWalker::insertPartialTableEntry(LongDescriptor &descriptor)
te.partial = true;
// The entry is global if there is no address space identifier
// to differentiate translation contexts
te.global = !mmu->hasUnprivRegime(
currState->el, currState->hcr.e2h);
te.isHyp = currState->isHyp;
te.global = !mmu->hasUnprivRegime(currState->regime);
te.asid = currState->asid;
te.vmid = currState->vmid;
te.N = descriptor.offsetBits();
@@ -2315,10 +2264,7 @@ TableWalker::insertPartialTableEntry(LongDescriptor &descriptor)
te.nstid = !currState->isSecure;
te.type = TypeTLB::unified;
if (currState->aarch64)
te.el = currState->el;
else
te.el = EL1;
te.regime = currState->regime;
te.xn = currState->xnTable;
te.pxn = currState->pxnTable;
@@ -2329,8 +2275,8 @@ TableWalker::insertPartialTableEntry(LongDescriptor &descriptor)
DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n",
te.N, te.pfn, te.size, te.global, te.valid);
DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d "
"vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn,
te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp,
"vmid:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn,
te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid,
te.nonCacheable, te.ns);
DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n",
descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()),
@@ -2349,7 +2295,6 @@ TableWalker::insertTableEntry(DescriptorBase &descriptor, bool long_descriptor)
// Create and fill a new page table entry
te.valid = true;
te.longDescFormat = long_descriptor;
te.isHyp = currState->isHyp;
te.asid = currState->asid;
te.vmid = currState->vmid;
te.N = descriptor.offsetBits();
@@ -2364,10 +2309,7 @@ TableWalker::insertTableEntry(DescriptorBase &descriptor, bool long_descriptor)
te.type = currState->mode == BaseMMU::Execute ?
TypeTLB::instruction : TypeTLB::data;
if (currState->aarch64)
te.el = currState->el;
else
te.el = EL1;
te.regime = currState->regime;
stats.pageSizes[pageSizeNtoStatBin(te.N)]++;
stats.requestOrigin[COMPLETED][currState->isFetch]++;
@@ -2405,8 +2347,8 @@ TableWalker::insertTableEntry(DescriptorBase &descriptor, bool long_descriptor)
DPRINTF(TLB, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n",
te.N, te.pfn, te.size, te.global, te.valid);
DPRINTF(TLB, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d "
"vmid:%d hyp:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn,
te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid, te.isHyp,
"vmid:%d nc:%d ns:%d\n", te.vpn, te.xn, te.pxn,
te.ap, static_cast<uint8_t>(te.domain), te.asid, te.vmid,
te.nonCacheable, te.ns);
DPRINTF(TLB, " - domain from L%d desc:%d data:%#x\n",
descriptor.lookupLevel, static_cast<uint8_t>(descriptor.domain()),

10
src/arch/arm/table_walker.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2016, 2019, 2021-2022 Arm Limited
* Copyright (c) 2010-2016, 2019, 2021-2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -647,7 +647,7 @@ class TableWalker : public ClockedObject
!currState->secureLookup)) {
return false; // ARM ARM issue C B3.6.3
} else if (currState->aarch64) {
if (!MMU::hasUnprivRegime(currState->el, currState->hcr.e2h)) {
if (!MMU::hasUnprivRegime(currState->regime)) {
// By default translations are treated as global
// in AArch64 for regimes without an unpriviledged
// component
@@ -810,6 +810,9 @@ class TableWalker : public ClockedObject
/** Current exception level */
ExceptionLevel el;
/** Current translation regime */
TranslationRegime regime;
/** Current physical address range in bits */
int physAddrRange;
@@ -822,7 +825,6 @@ class TableWalker : public ClockedObject
/** ASID that we're servicing the request under */
uint16_t asid;
vmid_t vmid;
bool isHyp;
/** Translation state for delayed requests */
BaseMMU::Translation *transState;
@@ -1105,7 +1107,7 @@ class TableWalker : public ClockedObject
Fault walk(const RequestPtr &req, ThreadContext *tc,
uint16_t asid, vmid_t _vmid,
bool hyp, BaseMMU::Mode mode, BaseMMU::Translation *_trans,
BaseMMU::Mode mode, BaseMMU::Translation *_trans,
bool timing, bool functional, bool secure,
MMU::ArmTranslationType tran_type, bool stage2,
const TlbEntry *walk_entry);

22
src/arch/arm/tlb.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013, 2016-2022 Arm Limited
* Copyright (c) 2010-2013, 2016-2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -160,17 +160,17 @@ TLB::lookup(const Lookup &lookup_data)
TlbEntry *retval = match(lookup_data);
DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d "
DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x secure %d "
"ppn %#x size: %#x pa: %#x ap:%d ns:%d nstid:%d g:%d asid: %d "
"el: %d\n",
"regime: %s\n",
lookup_data.va, lookup_data.asn, retval ? "hit" : "miss",
lookup_data.vmid, lookup_data.hyp, lookup_data.secure,
lookup_data.vmid, lookup_data.secure,
retval ? retval->pfn : 0, retval ? retval->size : 0,
retval ? retval->pAddr(lookup_data.va) : 0,
retval ? retval->ap : 0,
retval ? retval->ns : 0, retval ? retval->nstid : 0,
retval ? retval->global : 0, retval ? retval->asid : 0,
retval ? retval->el : 0);
retval ? regimeToStr(retval->regime) : 0);
// Updating stats if this was not a functional lookup
if (!lookup_data.functional) {
@@ -242,20 +242,20 @@ TLB::insert(TlbEntry &entry)
{
DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
" asid:%d vmid:%d N:%d global:%d valid:%d nc:%d xn:%d"
" ap:%#x domain:%#x ns:%d nstid:%d isHyp:%d\n", entry.pfn,
" ap:%#x domain:%#x ns:%d nstid:%d, regime: %s\n", entry.pfn,
entry.size, entry.vpn, entry.asid, entry.vmid, entry.N,
entry.global, entry.valid, entry.nonCacheable, entry.xn,
entry.ap, static_cast<uint8_t>(entry.domain), entry.ns, entry.nstid,
entry.isHyp);
entry.ap, static_cast<uint8_t>(entry.domain), entry.ns,
entry.nstid, regimeToStr(entry.regime));
if (table[size - 1].valid)
DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d vmn %d ppn %#x "
"size: %#x ap:%d ns:%d nstid:%d g:%d isHyp:%d el: %d\n",
"size: %#x ap:%d ns:%d nstid:%d g:%d regime: %s\n",
table[size-1].vpn << table[size-1].N, table[size-1].asid,
table[size-1].vmid, table[size-1].pfn << table[size-1].N,
table[size-1].size, table[size-1].ap, table[size-1].ns,
table[size-1].nstid, table[size-1].global, table[size-1].isHyp,
table[size-1].el);
table[size-1].nstid, table[size-1].global,
regimeToStr(table[size-1].regime));
// inserting to MRU position and evicting the LRU one
for (int i = size - 1; i > 0; --i)

35
src/arch/arm/tlbi_op.cc
View File

@@ -48,8 +48,6 @@ namespace ArmISA {
void
TLBIALL::operator()(ThreadContext* tc)
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
el2Enabled = EL2Enabled(tc);
currentEL = currEL(tc);
@@ -67,7 +65,7 @@ TLBIALL::match(TlbEntry* te, vmid_t vmid) const
{
return te->valid && secureLookup == !te->nstid &&
(te->vmid == vmid || el2Enabled) &&
te->checkELMatch(targetEL, inHost);
te->checkRegime(targetRegime);
}
void
@@ -99,8 +97,6 @@ DTLBIALL::match(TlbEntry* te, vmid_t vmid) const
void
TLBIALLEL::operator()(ThreadContext* tc)
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
getMMUPtr(tc)->flush(*this);
// If CheckerCPU is connected, need to notify it of a flush
@@ -114,14 +110,12 @@ bool
TLBIALLEL::match(TlbEntry* te, vmid_t vmid) const
{
return te->valid && secureLookup == !te->nstid &&
te->checkELMatch(targetEL, inHost);
te->checkRegime(targetRegime);
}
void
TLBIVMALL::operator()(ThreadContext* tc)
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
el2Enabled = EL2Enabled(tc);
getMMUPtr(tc)->flush(*this);
@@ -137,15 +131,13 @@ bool
TLBIVMALL::match(TlbEntry* te, vmid_t vmid) const
{
return te->valid && secureLookup == !te->nstid &&
te->checkELMatch(targetEL, inHost) &&
(te->vmid == vmid || !el2Enabled || (!stage2Flush() && inHost));
te->checkRegime(targetRegime) &&
(te->vmid == vmid || !el2Enabled || !useVMID(targetRegime));
}
void
TLBIASID::operator()(ThreadContext* tc)
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
el2Enabled = EL2Enabled(tc);
getMMUPtr(tc)->flushStage1(*this);
@@ -160,8 +152,8 @@ TLBIASID::match(TlbEntry* te, vmid_t vmid) const
{
return te->valid && te->asid == asid &&
secureLookup == !te->nstid &&
te->checkELMatch(targetEL, inHost) &&
(te->vmid == vmid || !el2Enabled || inHost);
te->checkRegime(targetRegime) &&
(te->vmid == vmid || !el2Enabled || !useVMID(targetRegime));
}
void
@@ -205,8 +197,7 @@ bool
TLBIALLN::match(TlbEntry* te, vmid_t vmid) const
{
return te->valid && te->nstid &&
te->isHyp == (targetEL == EL2) &&
te->checkELMatch(targetEL, false);
te->checkRegime(targetRegime);
}
TlbEntry::Lookup
@@ -216,11 +207,9 @@ TLBIMVAA::lookupGen(vmid_t vmid) const
lookup_data.va = sext<56>(addr);
lookup_data.ignoreAsn = true;
lookup_data.vmid = vmid;
lookup_data.hyp = targetEL == EL2;
lookup_data.secure = secureLookup;
lookup_data.functional = true;
lookup_data.targetEL = targetEL;
lookup_data.inHost = inHost;
lookup_data.targetRegime = targetRegime;
lookup_data.mode = BaseMMU::Read;
return lookup_data;
}
@@ -228,8 +217,6 @@ TLBIMVAA::lookupGen(vmid_t vmid) const
void
TLBIMVAA::operator()(ThreadContext* tc)
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
getMMUPtr(tc)->flushStage1(*this);
CheckerCPU *checker = tc->getCheckerCpuPtr();
@@ -254,11 +241,9 @@ TLBIMVA::lookupGen(vmid_t vmid) const
lookup_data.asn = asid;
lookup_data.ignoreAsn = false;
lookup_data.vmid = vmid;
lookup_data.hyp = targetEL == EL2;
lookup_data.secure = secureLookup;
lookup_data.functional = true;
lookup_data.targetEL = targetEL;
lookup_data.inHost = inHost;
lookup_data.targetRegime = targetRegime;
lookup_data.mode = BaseMMU::Read;
return lookup_data;
@@ -267,8 +252,6 @@ TLBIMVA::lookupGen(vmid_t vmid) const
void
TLBIMVA::operator()(ThreadContext* tc)
{
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
inHost = (hcr.tge == 1 && hcr.e2h == 1);
getMMUPtr(tc)->flushStage1(*this);
CheckerCPU *checker = tc->getCheckerCpuPtr();

99
src/arch/arm/tlbi_op.hh
View File

@@ -57,8 +57,8 @@ namespace ArmISA {
class TLBIOp
{
public:
TLBIOp(ExceptionLevel _targetEL, bool _secure)
: secureLookup(_secure), targetEL(_targetEL)
TLBIOp(TranslationRegime _target_regime, bool _secure)
: secureLookup(_secure), targetRegime(_target_regime)
{}
virtual ~TLBIOp() {}
@@ -101,15 +101,15 @@ class TLBIOp
}
bool secureLookup;
ExceptionLevel targetEL;
TranslationRegime targetRegime;
};
/** TLB Invalidate All */
class TLBIALL : public TLBIOp
{
public:
TLBIALL(ExceptionLevel _targetEL, bool _secure)
: TLBIOp(_targetEL, _secure), inHost(false), el2Enabled(false),
TLBIALL(TranslationRegime _target_regime, bool _secure)
: TLBIOp(_target_regime, _secure), el2Enabled(false),
currentEL(EL0)
{}
@@ -128,10 +128,9 @@ class TLBIALL : public TLBIOp
TLBIALL
makeStage2() const
{
return TLBIALL(EL1, secureLookup);
return TLBIALL(targetRegime, secureLookup);
}
bool inHost;
bool el2Enabled;
ExceptionLevel currentEL;
};
@@ -140,8 +139,8 @@ class TLBIALL : public TLBIOp
class ITLBIALL : public TLBIALL
{
public:
ITLBIALL(ExceptionLevel _targetEL, bool _secure)
: TLBIALL(_targetEL, _secure)
ITLBIALL(TranslationRegime _target_regime, bool _secure)
: TLBIALL(_target_regime, _secure)
{}
void broadcast(ThreadContext *tc) = delete;
@@ -155,8 +154,8 @@ class ITLBIALL : public TLBIALL
class DTLBIALL : public TLBIALL
{
public:
DTLBIALL(ExceptionLevel _targetEL, bool _secure)
: TLBIALL(_targetEL, _secure)
DTLBIALL(TranslationRegime _target_regime, bool _secure)
: TLBIALL(_target_regime, _secure)
{}
void broadcast(ThreadContext *tc) = delete;
@@ -170,8 +169,8 @@ class DTLBIALL : public TLBIALL
class TLBIALLEL : public TLBIOp
{
public:
TLBIALLEL(ExceptionLevel _targetEL, bool _secure)
: TLBIOp(_targetEL, _secure), inHost(false)
TLBIALLEL(TranslationRegime _target_regime, bool _secure)
: TLBIOp(_target_regime, _secure)
{}
void operator()(ThreadContext* tc) override;
@@ -182,24 +181,24 @@ class TLBIALLEL : public TLBIOp
stage2Flush() const override
{
// If we're targeting EL1 then flush stage2 as well
return targetEL == EL1;
return targetRegime == TranslationRegime::EL10 ||
targetRegime == TranslationRegime::EL20;
}
TLBIALLEL
makeStage2() const
{
return TLBIALLEL(EL1, secureLookup);
return TLBIALLEL(targetRegime, secureLookup);
}
bool inHost;
};
/** Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions */
class TLBIVMALL : public TLBIOp
{
public:
TLBIVMALL(ExceptionLevel _targetEL, bool _secure, bool _stage2)
: TLBIOp(_targetEL, _secure), inHost(false), el2Enabled(false),
TLBIVMALL(TranslationRegime _target_regime, bool _secure, bool _stage2)
: TLBIOp(_target_regime, _secure), el2Enabled(false),
stage2(_stage2)
{}
@@ -216,10 +215,9 @@ class TLBIVMALL : public TLBIOp
TLBIVMALL
makeStage2() const
{
return TLBIVMALL(EL1, secureLookup, false);
return TLBIVMALL(targetRegime, secureLookup, false);
}
bool inHost;
bool el2Enabled;
bool stage2;
};
@@ -228,8 +226,8 @@ class TLBIVMALL : public TLBIOp
class TLBIASID : public TLBIOp
{
public:
TLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
: TLBIOp(_targetEL, _secure), asid(_asid), inHost(false),
TLBIASID(TranslationRegime _target_regime, bool _secure, uint16_t _asid)
: TLBIOp(_target_regime, _secure), asid(_asid),
el2Enabled(false)
{}
@@ -238,7 +236,6 @@ class TLBIASID : public TLBIOp
bool match(TlbEntry *entry, vmid_t curr_vmid) const override;
uint16_t asid;
bool inHost;
bool el2Enabled;
};
@@ -246,8 +243,8 @@ class TLBIASID : public TLBIOp
class ITLBIASID : public TLBIASID
{
public:
ITLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
: TLBIASID(_targetEL, _secure, _asid)
ITLBIASID(TranslationRegime _target_regime, bool _secure, uint16_t _asid)
: TLBIASID(_target_regime, _secure, _asid)
{}
void broadcast(ThreadContext *tc) = delete;
@@ -261,8 +258,8 @@ class ITLBIASID : public TLBIASID
class DTLBIASID : public TLBIASID
{
public:
DTLBIASID(ExceptionLevel _targetEL, bool _secure, uint16_t _asid)
: TLBIASID(_targetEL, _secure, _asid)
DTLBIASID(TranslationRegime _target_regime, bool _secure, uint16_t _asid)
: TLBIASID(_target_regime, _secure, _asid)
{}
void broadcast(ThreadContext *tc) = delete;
@@ -276,8 +273,8 @@ class DTLBIASID : public TLBIASID
class TLBIALLN : public TLBIOp
{
public:
TLBIALLN(ExceptionLevel _targetEL)
: TLBIOp(_targetEL, false)
TLBIALLN(TranslationRegime _target_regime)
: TLBIOp(_target_regime, false)
{}
void operator()(ThreadContext* tc) override;
@@ -287,13 +284,13 @@ class TLBIALLN : public TLBIOp
bool
stage2Flush() const override
{
return targetEL != EL2;
return targetRegime != TranslationRegime::EL2;
}
TLBIALLN
makeStage2() const
{
return TLBIALLN(EL1);
return TLBIALLN(targetRegime);
}
};
@@ -303,9 +300,9 @@ class TLBIMVAA : public TLBIOp
protected:
TlbEntry::Lookup lookupGen(vmid_t vmid) const;
public:
TLBIMVAA(ExceptionLevel _targetEL, bool _secure,
TLBIMVAA(TranslationRegime _target_regime, bool _secure,
Addr _addr, bool last_level)
: TLBIOp(_targetEL, _secure), addr(_addr), inHost(false),
: TLBIOp(_target_regime, _secure), addr(_addr),
lastLevel(last_level)
{}
@@ -314,7 +311,6 @@ class TLBIMVAA : public TLBIOp
bool match(TlbEntry *entry, vmid_t curr_vmid) const override;
Addr addr;
bool inHost;
bool lastLevel;
};
@@ -325,10 +321,10 @@ class TLBIMVA : public TLBIOp
TlbEntry::Lookup lookupGen(vmid_t vmid) const;
public:
TLBIMVA(ExceptionLevel _targetEL, bool _secure,
TLBIMVA(TranslationRegime _target_regime, bool _secure,
Addr _addr, uint16_t _asid, bool last_level)
: TLBIOp(_targetEL, _secure), addr(_addr), asid(_asid),
inHost(false), lastLevel(last_level)
: TLBIOp(_target_regime, _secure), addr(_addr), asid(_asid),
lastLevel(last_level)
{}
void operator()(ThreadContext* tc) override;
@@ -337,7 +333,6 @@ class TLBIMVA : public TLBIOp
Addr addr;
uint16_t asid;
bool inHost;
bool lastLevel;
};
@@ -345,9 +340,9 @@ class TLBIMVA : public TLBIOp
class ITLBIMVA : public TLBIMVA
{
public:
ITLBIMVA(ExceptionLevel _targetEL, bool _secure,
ITLBIMVA(TranslationRegime _target_regime, bool _secure,
Addr _addr, uint16_t _asid)
: TLBIMVA(_targetEL, _secure, _addr, _asid, false)
: TLBIMVA(_target_regime, _secure, _addr, _asid, false)
{}
void broadcast(ThreadContext *tc) = delete;
@@ -361,9 +356,9 @@ class ITLBIMVA : public TLBIMVA
class DTLBIMVA : public TLBIMVA
{
public:
DTLBIMVA(ExceptionLevel _targetEL, bool _secure,
DTLBIMVA(TranslationRegime _target_regime, bool _secure,
Addr _addr, uint16_t _asid)
: TLBIMVA(_targetEL, _secure, _addr, _asid, false)
: TLBIMVA(_target_regime, _secure, _addr, _asid, false)
{}
void broadcast(ThreadContext *tc) = delete;
@@ -432,9 +427,9 @@ class TLBIRange
class TLBIIPA : public TLBIOp
{
public:
TLBIIPA(ExceptionLevel _targetEL, bool _secure, Addr _addr,
TLBIIPA(TranslationRegime _target_regime, bool _secure, Addr _addr,
bool last_level)
: TLBIOp(_targetEL, _secure), addr(_addr), lastLevel(last_level)
: TLBIOp(_target_regime, _secure), addr(_addr), lastLevel(last_level)
{}
void operator()(ThreadContext* tc) override;
@@ -455,7 +450,7 @@ class TLBIIPA : public TLBIOp
virtual TLBIMVAA
makeStage2() const
{
return TLBIMVAA(EL1, secureLookup, addr, lastLevel);
return TLBIMVAA(targetRegime, secureLookup, addr, lastLevel);
}
Addr addr;
@@ -466,10 +461,10 @@ class TLBIIPA : public TLBIOp
class TLBIRMVA : public TLBIRange, public TLBIMVA
{
public:
TLBIRMVA(ExceptionLevel _targetEL, bool _secure,
TLBIRMVA(TranslationRegime _target_regime, bool _secure,
RegVal val, uint16_t _asid, bool last_level)
: TLBIRange(val),
TLBIMVA(_targetEL, _secure, startAddress(), _asid, last_level)
TLBIMVA(_target_regime, _secure, startAddress(), _asid, last_level)
{}
bool match(TlbEntry *entry, vmid_t curr_vmid) const override;
@@ -479,10 +474,10 @@ class TLBIRMVA : public TLBIRange, public TLBIMVA
class TLBIRMVAA : public TLBIRange, public TLBIMVAA
{
public:
TLBIRMVAA(ExceptionLevel _targetEL, bool _secure,
TLBIRMVAA(TranslationRegime _target_regime, bool _secure,
RegVal val, bool last_level)
: TLBIRange(val),
TLBIMVAA(_targetEL, _secure, startAddress(), last_level)
TLBIMVAA(_target_regime, _secure, startAddress(), last_level)
{}
bool match(TlbEntry *entry, vmid_t curr_vmid) const override;
@@ -492,16 +487,16 @@ class TLBIRMVAA : public TLBIRange, public TLBIMVAA
class TLBIRIPA : public TLBIRange, public TLBIIPA
{
public:
TLBIRIPA(ExceptionLevel _targetEL, bool _secure,
TLBIRIPA(TranslationRegime _target_regime, bool _secure,
RegVal val, bool last_level)
: TLBIRange(val),
TLBIIPA(_targetEL, _secure, startAddress(), last_level)
TLBIIPA(_target_regime, _secure, startAddress(), last_level)
{}
virtual TLBIMVAA
makeStage2() const
{
return TLBIRMVAA(EL1, secureLookup, rangeData, lastLevel);
return TLBIRMVAA(targetRegime, secureLookup, rangeData, lastLevel);
}
};

44
src/arch/arm/tracers/tarmac_parser.cc
View File

@@ -625,37 +625,37 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
{ "at_s1e3r_xt", MISCREG_AT_S1E3R_Xt },
{ "at_s1e3w_xt", MISCREG_AT_S1E3W_Xt },
{ "tlbi_vmalle1is", MISCREG_TLBI_VMALLE1IS },
{ "tlbi_vae1is_xt", MISCREG_TLBI_VAE1IS_Xt },
{ "tlbi_aside1is_xt", MISCREG_TLBI_ASIDE1IS_Xt },
{ "tlbi_vaae1is_xt", MISCREG_TLBI_VAAE1IS_Xt },
{ "tlbi_vale1is_xt", MISCREG_TLBI_VALE1IS_Xt },
{ "tlbi_vaale1is_xt", MISCREG_TLBI_VAALE1IS_Xt },
{ "tlbi_vae1is", MISCREG_TLBI_VAE1IS },
{ "tlbi_aside1is", MISCREG_TLBI_ASIDE1IS },
{ "tlbi_vaae1is", MISCREG_TLBI_VAAE1IS },
{ "tlbi_vale1is", MISCREG_TLBI_VALE1IS },
{ "tlbi_vaale1is", MISCREG_TLBI_VAALE1IS },
{ "tlbi_vmalle1", MISCREG_TLBI_VMALLE1 },
{ "tlbi_vae1_xt", MISCREG_TLBI_VAE1_Xt },
{ "tlbi_aside1_xt", MISCREG_TLBI_ASIDE1_Xt },
{ "tlbi_vaae1_xt", MISCREG_TLBI_VAAE1_Xt },
{ "tlbi_vale1_xt", MISCREG_TLBI_VALE1_Xt },
{ "tlbi_vaale1_xt", MISCREG_TLBI_VAALE1_Xt },
{ "tlbi_ipas2e1is_xt", MISCREG_TLBI_IPAS2E1IS_Xt },
{ "tlbi_ipas2le1is_xt", MISCREG_TLBI_IPAS2LE1IS_Xt },
{ "tlbi_vae1", MISCREG_TLBI_VAE1 },
{ "tlbi_aside1", MISCREG_TLBI_ASIDE1 },
{ "tlbi_vaae1", MISCREG_TLBI_VAAE1 },
{ "tlbi_vale1", MISCREG_TLBI_VALE1 },
{ "tlbi_vaale1", MISCREG_TLBI_VAALE1 },
{ "tlbi_ipas2e1is", MISCREG_TLBI_IPAS2E1IS },
{ "tlbi_ipas2le1is", MISCREG_TLBI_IPAS2LE1IS },
{ "tlbi_alle2is", MISCREG_TLBI_ALLE2IS },
{ "tlbi_vae2is_xt", MISCREG_TLBI_VAE2IS_Xt },
{ "tlbi_vae2is", MISCREG_TLBI_VAE2IS },
{ "tlbi_alle1is", MISCREG_TLBI_ALLE1IS },
{ "tlbi_vale2is_xt", MISCREG_TLBI_VALE2IS_Xt },
{ "tlbi_vale2is", MISCREG_TLBI_VALE2IS },
{ "tlbi_vmalls12e1is", MISCREG_TLBI_VMALLS12E1IS },
{ "tlbi_ipas2e1_xt", MISCREG_TLBI_IPAS2E1_Xt },
{ "tlbi_ipas2le1_xt", MISCREG_TLBI_IPAS2LE1_Xt },
{ "tlbi_ipas2e1", MISCREG_TLBI_IPAS2E1 },
{ "tlbi_ipas2le1", MISCREG_TLBI_IPAS2LE1 },
{ "tlbi_alle2", MISCREG_TLBI_ALLE2 },
{ "tlbi_vae2_xt", MISCREG_TLBI_VAE2_Xt },
{ "tlbi_vae2", MISCREG_TLBI_VAE2 },
{ "tlbi_alle1", MISCREG_TLBI_ALLE1 },
{ "tlbi_vale2_xt", MISCREG_TLBI_VALE2_Xt },
{ "tlbi_vale2", MISCREG_TLBI_VALE2 },
{ "tlbi_vmalls12e1", MISCREG_TLBI_VMALLS12E1 },
{ "tlbi_alle3is", MISCREG_TLBI_ALLE3IS },
{ "tlbi_vae3is_xt", MISCREG_TLBI_VAE3IS_Xt },
{ "tlbi_vale3is_xt", MISCREG_TLBI_VALE3IS_Xt },
{ "tlbi_vae3is", MISCREG_TLBI_VAE3IS },
{ "tlbi_vale3is", MISCREG_TLBI_VALE3IS },
{ "tlbi_alle3", MISCREG_TLBI_ALLE3 },
{ "tlbi_vae3_xt", MISCREG_TLBI_VAE3_Xt },
{ "tlbi_vale3_xt", MISCREG_TLBI_VALE3_Xt },
{ "tlbi_vae3", MISCREG_TLBI_VAE3 },
{ "tlbi_vale3", MISCREG_TLBI_VALE3 },
{ "pmintenset_el1", MISCREG_PMINTENSET_EL1 },
{ "pmintenclr_el1", MISCREG_PMINTENCLR_EL1 },
{ "pmcr_el0", MISCREG_PMCR_EL0 },

25
src/arch/arm/types.hh
View File

@@ -276,6 +276,14 @@ namespace ArmISA
EL3
};
enum class TranslationRegime
{
EL10,
EL20,
EL2,
EL3
};
enum OperatingMode
{
MODE_EL0T = 0x0,
@@ -462,6 +470,23 @@ namespace ArmISA
}
}
static inline const char*
regimeToStr(TranslationRegime regime)
{
switch (regime) {
case TranslationRegime::EL10:
return "EL10";
case TranslationRegime::EL20:
return "EL20";
case TranslationRegime::EL2:
return "EL2";
case TranslationRegime::EL3:
return "EL3";
default:
GEM5_UNREACHABLE;
}
}
constexpr unsigned MaxSveVecLenInBits = 2048;
static_assert(MaxSveVecLenInBits >= 128 &&
MaxSveVecLenInBits <= 2048 &&

37
src/arch/arm/utility.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2009-2014, 2016-2020, 2022-2023 Arm Limited
* Copyright (c) 2009-2014, 2016-2020, 2022-2024 Arm Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -1366,5 +1366,40 @@ isHcrxEL2Enabled(ThreadContext *tc)
return EL2Enabled(tc);
}
TranslationRegime
translationRegime(ThreadContext *tc, ExceptionLevel el)
{
switch (el) {
case EL3:
return TranslationRegime::EL3;
case EL2:
return ELIsInHost(tc, EL2) ?
TranslationRegime::EL20 : TranslationRegime::EL2;
case EL1:
return TranslationRegime::EL10;
case EL0:
return ELIsInHost(tc, EL0) ?
TranslationRegime::EL20 : TranslationRegime::EL10;
default:
panic("Invalid ExceptionLevel\n");
}
}
ExceptionLevel
translationEl(TranslationRegime regime)
{
switch (regime) {
case TranslationRegime::EL10:
return EL1;
case TranslationRegime::EL20:
case TranslationRegime::EL2:
return EL2;
case TranslationRegime::EL3:
return EL3;
default:
return EL1;
}
}
} // namespace ArmISA
} // namespace gem5

9
src/arch/arm/utility.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2013, 2016-2020, 2022-2023 Arm Limited
* Copyright (c) 2010, 2012-2013, 2016-2020, 2022-2024 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -367,10 +367,13 @@ void syncVecElemsToRegs(ThreadContext *tc);
bool fgtEnabled(ThreadContext *tc);
bool isHcrxEL2Enabled(ThreadContext *tc);
TranslationRegime translationRegime(ThreadContext *tc, ExceptionLevel el);
ExceptionLevel translationEl(TranslationRegime regime);
static inline bool
useVMID(ExceptionLevel el, bool in_host)
useVMID(TranslationRegime regime)
{
return el == EL1 || (el == EL0 && !in_host);
return regime == TranslationRegime::EL10;
}
} // namespace ArmISA

3
src/dev/storage/ide_ctrl.hh
View File

@@ -96,7 +96,8 @@ class IdeController : public PciDevice
/* 0x48 */ Register8 udmaControl = {"udma control"};
/* 0x49 */ RegisterRaz raz1 = {"raz1", 1};
/* 0x4a-0x4b */ Register16 udmaTiming = {"udma timing"};
/* 0x4c-... */ RegisterRaz raz2 = {"raz2", PCI_CONFIG_SIZE - 0x4c};
/* 0x4c-... */ RegisterRaz raz2 =
{"raz2", (PCI_CONFIG_SIZE + 1) - 0x4c};
void serialize(CheckpointOut &cp) const;
void unserialize(CheckpointIn &cp);