458c98082c
This is the final step in the transformation process. We limit the use of the "managing Exception Level" for a translation in favour of the more standard "Translation Regime" This greatly simplifies our code, especially with VHE where the managing el (EL2) could handle to different translation regimes (EL and EL2&0). We can therefore remove the isHost flag wherever it got used. That case is automatically handled by the proper regime value (EL2&0) Change-Id: Iafd1d2ce4757cfa6598656759694e5e7b05267ad Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
484 lines
16 KiB
C++
484 lines
16 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013, 2021, 2023 Arm Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ARM_PAGETABLE_H__
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#define __ARCH_ARM_PAGETABLE_H__
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#include <cstdint>
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#include "arch/arm/page_size.hh"
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#include "arch/arm/types.hh"
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#include "arch/arm/utility.hh"
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#include "arch/generic/mmu.hh"
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#include "enums/TypeTLB.hh"
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#include "enums/ArmLookupLevel.hh"
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#include "sim/serialize.hh"
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namespace gem5
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{
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namespace ArmISA
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{
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// Granule sizes
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enum GrainSize
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{
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Grain4KB = 12,
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Grain16KB = 14,
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Grain64KB = 16,
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ReservedGrain = 0
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};
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extern const GrainSize GrainMap_tg0[];
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extern const GrainSize GrainMap_tg1[];
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// Max. physical address range in bits supported by the architecture
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const unsigned MaxPhysAddrRange = 52;
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// ITB/DTB page table entry
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struct PTE
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{
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void serialize(CheckpointOut &cp) const
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{
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panic("Need to implement PTE serialization\n");
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}
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void unserialize(CheckpointIn &cp)
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{
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panic("Need to implement PTE serialization\n");
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}
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};
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struct PageTableOps
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{
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typedef enums::ArmLookupLevel LookupLevel;
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typedef int64_t pte_t;
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virtual bool isValid(pte_t pte, unsigned level) const = 0;
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virtual bool isLeaf(pte_t pte, unsigned level) const = 0;
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virtual bool isWritable(pte_t pte, unsigned level, bool stage2) const = 0;
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virtual Addr nextLevelPointer(pte_t pte, unsigned level) const = 0;
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virtual Addr index(Addr va, unsigned level, int tsz) const = 0;
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virtual Addr pageMask(pte_t pte, unsigned level) const = 0;
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virtual unsigned walkBits(unsigned level) const = 0;
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virtual LookupLevel firstLevel(uint8_t tsz) const = 0;
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virtual LookupLevel firstS2Level(uint8_t sl0) const = 0;
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virtual LookupLevel lastLevel() const = 0;
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Addr walkMask(unsigned level) const;
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};
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struct V7LPageTableOps : public PageTableOps
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{
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bool isValid(pte_t pte, unsigned level) const override;
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bool isLeaf(pte_t pte, unsigned level) const override;
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bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
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Addr nextLevelPointer(pte_t pte, unsigned level) const override;
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Addr index(Addr va, unsigned level, int tsz) const override;
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Addr pageMask(pte_t pte, unsigned level) const override;
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unsigned walkBits(unsigned level) const override;
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LookupLevel firstLevel(uint8_t tsz) const override;
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LookupLevel lastLevel() const override;
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};
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struct V8PageTableOps4k : public PageTableOps
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{
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bool isValid(pte_t pte, unsigned level) const override;
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bool isLeaf(pte_t pte, unsigned level) const override;
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bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
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Addr nextLevelPointer(pte_t pte, unsigned level) const override;
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Addr index(Addr va, unsigned level, int tsz) const override;
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Addr pageMask(pte_t pte, unsigned level) const override;
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unsigned walkBits(unsigned level) const override;
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LookupLevel firstLevel(uint8_t tsz) const override;
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LookupLevel firstS2Level(uint8_t sl0) const override;
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LookupLevel lastLevel() const override;
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};
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struct V8PageTableOps16k : public PageTableOps
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{
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bool isValid(pte_t pte, unsigned level) const override;
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bool isLeaf(pte_t pte, unsigned level) const override;
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bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
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Addr nextLevelPointer(pte_t pte, unsigned level) const override;
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Addr index(Addr va, unsigned level, int tsz) const override;
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Addr pageMask(pte_t pte, unsigned level) const override;
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unsigned walkBits(unsigned level) const override;
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LookupLevel firstLevel(uint8_t tsz) const override;
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LookupLevel firstS2Level(uint8_t sl0) const override;
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LookupLevel lastLevel() const override;
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};
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struct V8PageTableOps64k : public PageTableOps
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{
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bool isValid(pte_t pte, unsigned level) const override;
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bool isLeaf(pte_t pte, unsigned level) const override;
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bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
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Addr nextLevelPointer(pte_t pte, unsigned level) const override;
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Addr index(Addr va, unsigned level, int tsz) const override;
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Addr pageMask(pte_t pte, unsigned level) const override;
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unsigned walkBits(unsigned level) const override;
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LookupLevel firstLevel(uint8_t tsz) const override;
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LookupLevel firstS2Level(uint8_t sl0) const override;
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LookupLevel lastLevel() const override;
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};
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// ITB/DTB table entry
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struct TlbEntry : public Serializable
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{
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public:
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typedef enums::ArmLookupLevel LookupLevel;
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enum class MemoryType : std::uint8_t
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{
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StronglyOrdered,
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Device,
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Normal
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};
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enum class DomainType : std::uint8_t
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{
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NoAccess = 0,
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Client,
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Reserved,
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Manager
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};
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struct Lookup
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{
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// virtual address
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Addr va = 0;
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// lookup size:
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// * != 0 -> this is a range based lookup.
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// end_address = va + size
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// * == 0 -> This is a normal lookup. size should
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// be ignored
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Addr size = 0;
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// context id/address space id to use
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uint16_t asn = 0;
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// if on lookup asn should be ignored
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bool ignoreAsn = false;
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// The virtual machine ID used for stage 2 translation
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vmid_t vmid = 0;
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// if the lookup is secure
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bool secure = false;
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// if the lookup should modify state
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bool functional = false;
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// selecting the translation regime
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TranslationRegime targetRegime = TranslationRegime::EL10;
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// mode to differentiate between read/writes/fetches.
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BaseMMU::Mode mode = BaseMMU::Read;
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};
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// Matching variables
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Addr pfn;
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Addr size; // Size of this entry, == Type of TLB Rec
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Addr vpn; // Virtual Page Number
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uint64_t attributes; // Memory attributes formatted for PAR
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LookupLevel lookupLevel; // Lookup level where the descriptor was fetched
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// from. Used to set the FSR for faults
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// occurring while the long desc. format is in
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// use (AArch32 w/ LPAE and AArch64)
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uint16_t asid; // Address Space Identifier
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vmid_t vmid; // Virtual machine Identifier
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GrainSize tg; // Translation Granule Size
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uint8_t N; // Number of bits in pagesize
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uint8_t innerAttrs;
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uint8_t outerAttrs;
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uint8_t ap; // Access permissions bits
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uint8_t hap; // Hyp access permissions bits
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DomainType domain; // Access Domain
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MemoryType mtype;
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// True if the long descriptor format is used for this entry (LPAE only)
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bool longDescFormat; // @todo use this in the update attribute bethod
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bool global;
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bool valid;
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// True if the entry targets the non-secure physical address space
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bool ns;
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// True if the entry was brought in from a non-secure page table
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bool nstid;
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// Translation regime on insert, AARCH64 EL0&1, AARCH32 -> el=1
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TranslationRegime regime;
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// This is used to distinguish between instruction and data entries
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// in unified TLBs
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TypeTLB type;
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// True if the entry is caching a partial translation (a table walk)
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bool partial;
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// Type of memory
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bool nonCacheable; // Can we wrap this in mtype?
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// Memory Attributes
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bool shareable;
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bool outerShareable;
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// Access permissions
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bool xn; // Execute Never
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bool pxn; // Privileged Execute Never (LPAE only)
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//Construct an entry that maps to physical address addr for SE mode
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TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr,
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bool uncacheable, bool read_only) :
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pfn(_paddr >> PageShift), size(PageBytes - 1), vpn(_vaddr >> PageShift),
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attributes(0), lookupLevel(LookupLevel::L1),
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asid(_asn), vmid(0), tg(Grain4KB), N(0),
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innerAttrs(0), outerAttrs(0), ap(read_only ? 0x3 : 0), hap(0x3),
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domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
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longDescFormat(false), global(false), valid(true),
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ns(true), nstid(true), regime(TranslationRegime::EL10),
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type(TypeTLB::unified), partial(false),
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nonCacheable(uncacheable),
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shareable(false), outerShareable(false), xn(0), pxn(0)
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{
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// no restrictions by default, hap = 0x3
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// @todo Check the memory type
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if (read_only)
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warn("ARM TlbEntry does not support read-only mappings\n");
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}
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TlbEntry() :
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pfn(0), size(0), vpn(0), attributes(0), lookupLevel(LookupLevel::L1),
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asid(0), vmid(0), tg(ReservedGrain), N(0),
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innerAttrs(0), outerAttrs(0), ap(0), hap(0x3),
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domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
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longDescFormat(false), global(false), valid(false),
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ns(true), nstid(true), regime(TranslationRegime::EL10),
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type(TypeTLB::unified), partial(false), nonCacheable(false),
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shareable(false), outerShareable(false), xn(0), pxn(0)
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{
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// no restrictions by default, hap = 0x3
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// @todo Check the memory type
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}
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void
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updateVaddr(Addr new_vaddr)
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{
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vpn = new_vaddr >> PageShift;
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}
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Addr
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pageStart() const
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{
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return pfn << PageShift;
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}
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bool
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matchAddress(const Lookup &lookup) const
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{
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Addr page_addr = vpn << N;
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if (lookup.size) {
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// This is a range based loookup
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return lookup.va <= page_addr + size &&
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lookup.va + lookup.size > page_addr;
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} else {
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// This is a normal lookup
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return lookup.va >= page_addr && lookup.va <= page_addr + size;
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}
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}
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bool
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match(const Lookup &lookup) const
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{
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bool match = false;
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if (valid && matchAddress(lookup) &&
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(lookup.secure == !nstid))
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{
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match = checkRegime(lookup.targetRegime);
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if (match && !lookup.ignoreAsn) {
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match = global || (lookup.asn == asid);
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}
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if (match && useVMID(lookup.targetRegime)) {
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match = lookup.vmid == vmid;
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}
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}
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return match;
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}
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bool
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checkRegime(TranslationRegime target_regime) const
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{
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return regime == target_regime;
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}
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Addr
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pAddr(Addr va) const
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{
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return (pfn << N) | (va & size);
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}
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void
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updateAttributes()
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{
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uint64_t mask;
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uint64_t newBits;
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// chec bit 11 to determine if its currently LPAE or VMSA format.
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if ( attributes & (1 << 11) ) {
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newBits = ((outerShareable ? 0x2 :
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shareable ? 0x3 : 0) << 7);
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mask = 0x180;
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} else {
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/** Formatting for Physical Address Register (PAR)
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* Only including lower bits (TLB info here)
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* PAR (32-bit format):
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* PA [31:12]
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* LPAE [11] (Large Physical Address Extension)
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* TLB info [10:1]
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* NOS [10] (Not Outer Sharable)
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* NS [9] (Non-Secure)
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* -- [8] (Implementation Defined)
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* SH [7] (Sharable)
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* Inner[6:4](Inner memory attributes)
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* Outer[3:2](Outer memory attributes)
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* SS [1] (SuperSection)
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* F [0] (Fault, Fault Status in [6:1] if faulted)
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*/
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newBits = ((outerShareable ? 0:1) << 10) |
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((shareable ? 1:0) << 7) |
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(innerAttrs << 4) |
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(outerAttrs << 2);
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// TODO: Supersection bit
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mask = 0x4FC;
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}
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// common bits
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newBits |= ns << 9; // NS bit
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mask |= 1 << 9;
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// add in the new bits
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attributes &= ~mask;
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attributes |= newBits;
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}
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void
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setAttributes(bool lpae)
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{
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attributes = lpae ? (1 << 11) : 0;
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updateAttributes();
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}
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std::string
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print() const
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{
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return csprintf("%#x, asn %d vmn %d ppn %#x size: %#x ap:%d "
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"ns:%d nstid:%d g:%d regime:%s", vpn << N, asid, vmid,
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pfn << N, size, ap, ns, nstid, global,
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regimeToStr(regime));
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}
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void
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serialize(CheckpointOut &cp) const override
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{
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SERIALIZE_SCALAR(longDescFormat);
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SERIALIZE_SCALAR(pfn);
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SERIALIZE_SCALAR(size);
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SERIALIZE_SCALAR(vpn);
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SERIALIZE_SCALAR(asid);
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SERIALIZE_SCALAR(vmid);
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SERIALIZE_SCALAR(N);
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SERIALIZE_SCALAR(global);
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SERIALIZE_SCALAR(valid);
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SERIALIZE_SCALAR(ns);
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SERIALIZE_SCALAR(nstid);
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SERIALIZE_ENUM(type);
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SERIALIZE_SCALAR(nonCacheable);
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SERIALIZE_ENUM(lookupLevel);
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SERIALIZE_ENUM(mtype);
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SERIALIZE_SCALAR(innerAttrs);
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SERIALIZE_SCALAR(outerAttrs);
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SERIALIZE_SCALAR(shareable);
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SERIALIZE_SCALAR(outerShareable);
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SERIALIZE_SCALAR(attributes);
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SERIALIZE_SCALAR(xn);
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SERIALIZE_SCALAR(pxn);
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SERIALIZE_SCALAR(ap);
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SERIALIZE_SCALAR(hap);
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uint8_t domain_ = static_cast<uint8_t>(domain);
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paramOut(cp, "domain", domain_);
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}
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void
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unserialize(CheckpointIn &cp) override
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{
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UNSERIALIZE_SCALAR(longDescFormat);
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UNSERIALIZE_SCALAR(pfn);
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UNSERIALIZE_SCALAR(size);
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UNSERIALIZE_SCALAR(vpn);
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UNSERIALIZE_SCALAR(asid);
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UNSERIALIZE_SCALAR(vmid);
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UNSERIALIZE_SCALAR(N);
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UNSERIALIZE_SCALAR(global);
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UNSERIALIZE_SCALAR(valid);
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UNSERIALIZE_SCALAR(ns);
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UNSERIALIZE_SCALAR(nstid);
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UNSERIALIZE_ENUM(type);
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UNSERIALIZE_SCALAR(nonCacheable);
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UNSERIALIZE_ENUM(lookupLevel);
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UNSERIALIZE_ENUM(mtype);
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UNSERIALIZE_SCALAR(innerAttrs);
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UNSERIALIZE_SCALAR(outerAttrs);
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UNSERIALIZE_SCALAR(shareable);
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UNSERIALIZE_SCALAR(outerShareable);
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UNSERIALIZE_SCALAR(attributes);
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UNSERIALIZE_SCALAR(xn);
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UNSERIALIZE_SCALAR(pxn);
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UNSERIALIZE_SCALAR(ap);
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UNSERIALIZE_SCALAR(hap);
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uint8_t domain_;
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paramIn(cp, "domain", domain_);
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domain = static_cast<DomainType>(domain_);
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}
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};
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const PageTableOps *getPageTableOps(GrainSize trans_granule);
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} // namespace ArmISA
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} // namespace gem5
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#endif // __ARCH_ARM_PAGETABLE_H__
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