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fastmodel: add interface to update system counter freq

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This CL set the cntfrq and system counter frequency at once from python
script. This aligns the fastmodel implementation to other part of gem5
CPU.

Change-Id: I78c9a7be801112844c03d2669a94d57015136d16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40278
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Earl Ou
2021-02-01 10:24:44 +08:00
parent 16c1986fe2
commit f0924fc39b
10 changed files with 55 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
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@@ -41,6 +41,8 @@ CortexA76::initState()
{
for (auto *tc : threadContexts)
tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, params().cntfrq);
evs_base_cpu->setSysCounterFrq(cluster->params().cntfrq);
}
void

8
src/arch/arm/fastmodel/CortexA76/evs.cc
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@@ -44,6 +44,13 @@ ScxEvsCortexA76<Types>::setClkPeriod(Tick clk_period)
clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
}
template <class Types>
void
ScxEvsCortexA76<Types>::setSysCounterFrq(uint64_t sys_counter_frq)
{
periphClockRateControl->set_mul_div(sys_counter_frq, 1);
}
template <class Types>
void
ScxEvsCortexA76<Types>::setCluster(SimObject *cluster)
@@ -86,6 +93,7 @@ ScxEvsCortexA76<Types>::ScxEvsCortexA76(
}
clockRateControl.bind(this->clock_rate_s);
periphClockRateControl.bind(this->periph_clock_rate_s);
}
template <class Types>

3
src/arch/arm/fastmodel/CortexA76/evs.hh
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@@ -63,6 +63,7 @@ class ScxEvsCortexA76 : public Types::Base, public Iris::BaseCpuEvs
SC_HAS_PROCESS(ScxEvsCortexA76);
ClockRateControlInitiatorSocket clockRateControl;
ClockRateControlInitiatorSocket periphClockRateControl;
typedef sc_gem5::TlmTargetBaseWrapper<
64, svp_gicv3_comms::gicv3_comms_fw_if,
@@ -105,6 +106,8 @@ class ScxEvsCortexA76 : public Types::Base, public Iris::BaseCpuEvs
void setClkPeriod(Tick clk_period) override;
void setSysCounterFrq(uint64_t sys_counter_frq) override;
void setCluster(SimObject *cluster) override;
};

9
src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
View File

@@ -35,7 +35,7 @@ component CortexA76x1
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
clockDivPeriph : ClockDivider(mul=0x01800000);
clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@ component CortexA76x1
clockDiv.rate.set64(mul, div);
}
}
slave port<ExportedClockRateControl> periph_clock_rate_s
{
behavior set_mul_div(uint64_t mul, uint64_t div)
{
clockDivPeriph.rate.set64(mul, div);
}
}
slave port<GICv3Comms> redistributor[1];
// External ports for CPU-to-GIC signals

9
src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
View File

@@ -35,7 +35,7 @@ component CortexA76x2
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
clockDivPeriph : ClockDivider(mul=0x01800000);
clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@ component CortexA76x2
clockDiv.rate.set64(mul, div);
}
}
slave port<ExportedClockRateControl> periph_clock_rate_s
{
behavior set_mul_div(uint64_t mul, uint64_t div)
{
clockDivPeriph.rate.set64(mul, div);
}
}
slave port<GICv3Comms> redistributor[2];
// External ports for CPU-to-GIC signals

9
src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
View File

@@ -35,7 +35,7 @@ component CortexA76x3
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
clockDivPeriph : ClockDivider(mul=0x01800000);
clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@ component CortexA76x3
clockDiv.rate.set64(mul, div);
}
}
slave port<ExportedClockRateControl> periph_clock_rate_s
{
behavior set_mul_div(uint64_t mul, uint64_t div)
{
clockDivPeriph.rate.set64(mul, div);
}
}
slave port<GICv3Comms> redistributor[3];
// External ports for CPU-to-GIC signals

9
src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
View File

@@ -35,7 +35,7 @@ component CortexA76x4
// Clocks.
clock1Hz : MasterClock();
clockDiv : ClockDivider();
clockDivPeriph : ClockDivider(mul=0x01800000);
clockDivPeriph : ClockDivider();
}
connection
@@ -77,6 +77,13 @@ component CortexA76x4
clockDiv.rate.set64(mul, div);
}
}
slave port<ExportedClockRateControl> periph_clock_rate_s
{
behavior set_mul_div(uint64_t mul, uint64_t div)
{
clockDivPeriph.rate.set64(mul, div);
}
}
slave port<GICv3Comms> redistributor[4];
// External ports for CPU-to-GIC signals

7
src/arch/arm/fastmodel/CortexR52/evs.cc
View File

@@ -43,6 +43,13 @@ ScxEvsCortexR52<Types>::setClkPeriod(Tick clk_period)
clockRateControl->set_mul_div(SimClock::Int::s, clk_period);
}
template <class Types>
void
ScxEvsCortexR52<Types>::setSysCounterFrq(uint64_t sys_counter_frq)
{
panic("Not implemented for R52.");
}
template <class Types>
void
ScxEvsCortexR52<Types>::setCluster(SimObject *cluster)

2
src/arch/arm/fastmodel/CortexR52/evs.hh
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@@ -140,6 +140,8 @@ class ScxEvsCortexR52 : public Types::Base, public Iris::BaseCpuEvs
void setClkPeriod(Tick clk_period) override;
void setSysCounterFrq(uint64_t sys_counter_frq) override;
void setCluster(SimObject *cluster) override;
};

1
src/arch/arm/fastmodel/iris/cpu.hh
View File

@@ -44,6 +44,7 @@ class BaseCpuEvs
public:
virtual void sendFunc(PacketPtr pkt) = 0;
virtual void setClkPeriod(Tick clk_period) = 0;
virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
virtual void setCluster(SimObject *cluster) = 0;
};